This correspondence deals with the application of a bit slice microprocessor to a satellite born packet switch. A system architecture for accomplishing this task is proposed, and the performance of the packet switch is evaluated by obtaining an upper bound on the system throughput.

The design and performance evaluation of a single microprocessor based packet switch for use on-board a satellite are presented. The primary design criterion is to maximize the system throughput. A number of protocols and their impact on the switch design are discussed. System and processor hardware architectures are described. The flow charts of the software required to accomplish the essential functions are presented and modification needed for use in a multisatellite network are also indicated. Maximum throughput attainable is calculated. Desirable characteristics of microprocessors for this application are pointed out. A queue theoretic model of the packet switch has been developed. Analytical relationships of the average waiting times and the queue sizes at the queues and the overall average response time with the various design parameters of the switch have been obtained. A number of graphs showing the effect of variation in the number of input and output lines, data rates, destination fucntions, speed of output lines and some other design parameters on the performance of the switch are presented and discussed.