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Aadil Amoura

dblp:271/7468 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
floorplanning		 0.011998
Timing Driven Floorplanning on Programmable Hierarchical Targets · FPGA 1998
Electronic design automation
physical design		 0.011998
Timing Driven Floorplanning on Programmable Hierarchical Targets · FPGA 1998
Electronic design automation › physical design › floorplanning
timing-driven floorplanning		 0.011998
Timing Driven Floorplanning on Programmable Hierarchical Targets · FPGA 1998
Electronic design automation
timing analysis		 0.011998
Timing Driven Floorplanning on Programmable Hierarchical Targets · FPGA 1998
Electronic design automation › physical design
timing optimization		 0.011998
Timing Driven Floorplanning on Programmable Hierarchical Targets · FPGA 1998

Methods — techniques the papers use, named apart from their topics

greedy floorplanning · 0.0cone structuring · 0.0
YearPublicationVenuePosition
1998 Timing Driven Floorplanning on Programmable Hierarchical Targets
abstract
The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.
S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier
 FPGA2