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Nicholas Weiner

dblp:271/8853 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis		 0.011989
Timing Analysis in a Logic Synthesis Environment · DAC 1989
Electronic design automation
timing analysis		 0.011989
Timing Analysis in a Logic Synthesis Environment · DAC 1989
Electronic design automation › logic synthesis › performance-driven synthesis
timing-driven synthesis		 0.011989
Timing Analysis in a Logic Synthesis Environment · DAC 1989

Methods — techniques the papers use, named apart from their topics

timing analysis · 0.0
YearPublicationVenuePosition
1989 Timing Analysis in a Logic Synthesis Environment
abstract
A goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. The design process involves repeated timing analyses followed by appropriate modifications.
Nicholas Weiner, Alberto L. Sangiovanni-Vincentelli
 DAC1