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Zaheer M. Ali

dblp:272/1912 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1978
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.011978
A High-Speed FFT Processor · IEEE Trans. Commun. 1978
Hardware accelerators and domain-specific architectures › signal processing accelerator
FFT processor		 0.011978
A High-Speed FFT Processor · IEEE Trans. Commun. 1978
Hardware accelerators and domain-specific architectures
signal processing accelerator		 0.011978
A High-Speed FFT Processor · IEEE Trans. Commun. 1978

Methods — techniques the papers use, named apart from their topics

real-time address generation · 0.0parallel multiplier · 0.0
YearPublicationVenuePosition
1978 A High-Speed FFT Processor
abstract
A high-speed, low-power, fast Fourier transform (FFT) processor is described in this paper. The FFT processor is designed around parallel arithmetic functions (16 by 16 multiplier and 16-bit adders) and can operate up to a 17.0-MHz clock rate. It performs a 128-point FFT in 250 μs at 16-MHz clock rate and therefore can be used for applications such as frequency-division multiplexing/timedivision multiplexing (FDM/TDM) transmultiplexer. The processor was designed and tested according to the design specifications. Its standalone feature permits its use in a variety of systems employing spectral analysis. The high-speed requirements are met by a real-time address generation scheme. The design can be used for a higher order FFT by providing extra memory space.
Zaheer M. Ali
 IEEE Trans. Commun.1