A stray-insensitive biphase SC realization of an all-pole filter of any desired order is first obtained in the ladder form with all the SCs of equal value. These equal-valued SCs are then replaced by a single time-shared SC. Like any other time-multiplexed circuit, this circuit also requires an increased number of clock phases. Thus against an increase in the die area to generate a multiphase clock on the chip, there is a saving due to the reduction in the total capacitance. One such fifth-order low-pass filter is designed and tested with discrete components to verify its performance.

A simple active equalizer network employing two operational amplifiers (OA's), five resistors, and a pair of capacitors is presented. The same network can be used for both amplitude and delay equalizations. Experimental results show that the circuit can be conveniently used for amplitude equalization in voice communications, and for delay equalization in private line data circuits.