Computation-in-Memory (CiM) is a promising solution to reduce the energy and latency caused by frequent data transfers between the processor and memory, a problem commonly referred to as the memory wall. For instance, comparing binary patterns to measure similarity is a common and challenging task in today’s emerging artificial intelligence applications. This can be implemented efficiently using Content Addressable Memory (CAM), which is well-suited for CiM-based acceleration of such tasks. To improve energy efficiency and performance, non-volatile memories (NVM) such as ReRAM (Redox-based RAM) can be utilized for the realization of CiMbased CAM. However, ReRAM is highly susceptible to process variations (PV), due to the immaturity of its process and inherent stochasticity. Moreover, the analog realization of CAM functionality using NVMs makes it more sensitive to these non-idealities. Conventional March tests, originally designed for memory fault detection, become ineffective in the presence of PV, which can alter ReCAM behavior and lead to test escapes. To address these challenges, this work systematically analyzes the impact of PV on ReCAM functionality. It proposes a generalized PV-aware March test that optimizes test patterns for both hard and PV-induced soft defects, achieving 100% defect coverage.

Brain-inspired Hyperdimensional Computing (HDC) is emerging as a compelling paradigm for learning at the edge because of its one-shot learning capability, inherent scalability, and exceptionally low computational overhead. While HDC is robust to noise, soft and hard memory faults in the memory components of HDC accelerator can still significantly degrade accuracy. Conventional error correction codes (ECC) are commonly used to mitigate such faults, but their associated overhead make them impractical for resource-constrained edge devices. In this paper, we present a novel memory-free error correction technique to enhance the fault tolerance of HDC systems without requiring any dedicated memory to store check-bits. This way, not only is the memory overhead and its associated constraints eliminated, but also the possibility of errors occurring within the Error-Correcting Code (ECC) check-bits themselves is omitted. Additionally, the proposed method is highly scalable, with minimal hardware overhead, and is therefore suitable for edge implementations. We validate the approach on an FPGA, demonstrating its practicality and effectiveness. Compared to the state-of-the-art correction methods, our memory-free design achieves $27 \times$ lower LUT utilization, more than $80 \times$ fewer registers and no DSP, BRAM, or latency at all. At the same time, it is capable of preserving inference accuracy under a $\mathbf{1 2} \boldsymbol{\times}$ higher fault possibility.

Memristor-based computation-in-memory (CiM) architectures address the growing computational demands of AI accelerators by enabling analog matrix-vector multiplication (MVM) directly within the memory array. Passive (selectorless) memristive crossbars are particularly attractive for such architectures due to their high density and compatibility with back-end-of-line fabrication. Here, AI model parameters are stored as memristor conductances, and MVM is performed in situ by activating multiple rows simultaneously and sensing the resulting column currents. As a result, column currents become the primary observable, making column-level fault detection more relevant for AI workloads than conventional March-based cell-level tests, which are specially time - and energy-intensive for passive crossbars due to specialized biasing methods. To address this, we propose a current-based testing methodology tailored to passive crossbars that detects and diagnoses faulty columns while accounting for non-idealities such as sneak-path currents, line resistance, and process variations. Faulty columns are detected by programming all cells to a uniform state and measuring column-current deviations, followed by targeted test patterns to estimate per-column fault density. On a $64 \times 64$ array, the proposed approach achieves 100% faulty column detection, 98% overall fault coverage, and a $2.3 \times$ speed-up in test time compared to conventional March tests. Hence, providing a fast and efficient solution for manufacturing screening of passive crossbars with sufficient diagnostic resolution to support systemlevel fault tolerance for AI applications.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing memory technologies. However, STT-MRAM faces reliability challenges, primarily due to stochastic switching, process variation, and manufacturing defects. These reliability challenges become even worse due to interconnect parasitic resistive-capacitive effects, potentially compromising the reliability of memory cells located far from the write driver. This can severely impair the manu-facturing yield and large-scale industrial adoption. Toaddressthis, we propose an interconnect-aware error correction coding (InterA-ECC), which provides non-uniform error correction to a different zone of the memory subarray. The proposed InterA-ECC strategy selectively applies robust error-correction code (ECC) to specific rows within the subarray rather than uniformly across all rows, reducing ECC parity bits while enhancing bit error rate resiliency in the most vulnerable memory zone.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Content Addressable Memory enables high-speed binary pattern matching and is widely used in various applications. Exploiting Resistive Random Access Memory (ReRAM) for CAM (ReCAM) realization offers advantages in terms of non-volatility, high density, and low power consumption using the Computation in Memory (CiM) concept. However, the unique defects of ReRAM combined with CMOS fabrication defects, introduce new faulty behaviors that complicate detection and diagnosis, thereby increasing the risk of test escapes and field failures. However, diagnosing faulty cells in ReCAM is crucial for analyzing failure mode, which helps improve manufacturing yield. It also promotes defect and fault tolerance both post-manufacturing and during runtime. Pinpointing faulty cells within the ReCAM array is particularly challenging, especially when all cells are connected to the same match-line (ML). Diagnosis also plays a critical role at runtime by enabling fault tolerance through mechanisms such as bypassing defective cells. This paper proposes a novel Design-for-Testability (DfT) approach for ReCAM diagnosis that utilizes infinitesimal voltage differences to identify the location of faulty cells. The proposed DfT circuitry and the accompanied diagnosis flow enhance diagnostic precision by enabling adjustable gain and sampling time in a multi-step process, effectively identifying faulty cells within the array. The simulation results of two distinct fault scenarios, applied to the binary patterns of all-match and all-mismatch conditions, demonstrate the effectiveness of the proposed DfT technique in achieving fine-grained fault detection across the ReCAM array. Furthermore, using this approach reduces the time complexity by more than half compared to the March-based approach with negligible overhead in area and power.

Compute-in-Memory (CiM) employing Non-Volatile Memory (NVM) technology is an emerging paradigm that promises higher power efficiency for important data-intensive computations. The performance, power, and resilience properties of emerging NVM technologies determine the efficiency of architectures built around processors and computational memories, and affect design decisions. Thus, fast exploration of the broad design space is necessary to assist decision-making. We present Sisyphus, the first cross-layer framework built to facilitate computer architecture research when such an exploration is required. Sisyphus incorporates detailed technology information for various CiM circuit designs based on STT-MRAM, ReRAM, and PCM technologies and integrates them in fast microarchitecture level system models in gem5 to evaluate performance, power, and resilience (through fault injection) across a large space of design options. Sisyphus’ holistic modeling enables the comprehensive evaluation of all efficiency aspects during the execution of actual workloads on the CPU-CiM architecture. This allows for comparisons to a baseline CPU-only system. In our experimental evaluation, we demonstrate how Sisyphus can derive conclusions regarding the prevalence of one NVM type over another, depending on the prioritized optimization aspect(s).

Measuring similarity between binary patterns is a key kernel in various data-intensive applications such as search engines and artificial intelligence (AI). However, due to the memory wall problem caused by frequent data transfers between processor cores and memory subsystems, executing these operations leads to high energy consumption and increased latency. One approach to mitigating this problem is to utilize Computing-in-Memory (CiM) architectures for the realization of Content-Addressable Memory (CAM) in such applications. Integrating Non-Volatile Memory (NVM) technologies can improve performance and energy efficiency. Redox-based Resistive Access Memory (ReRAM) is a promising candidate for implementation within NVM-based Content-Addressable Memory (CAM) due to its non-volatile nature, low power consumption, and highly distinct resistive levels. However, integrating NVM with conventional CMOS introduces unique fabrication challenges and failure mechanisms that are not seen in CMOS processes alone. Furthermore, the analog nature of CiM increases sensitivity to non-idealities in both ReRAM and CMOS, resulting in new fault behaviors that affect the quality of ReRAM-based CAM (ReCAM) blocks. Therefore, to ensure the high quality of the ReCAM functionality, this paper develops a March-like test algorithm tailored for the ReCAM array. The proposed March-like test algorithm is extendable and can achieve 100% fault coverage.

The demand for Artificial Intelligence (AI) and large AI models mandates high compute power, driving substantial increases in computational cost, both in terms of energy and hardware resources. From the hardware perspective, training these models typically relies on dataflow architectures such as Graphical Processing Unit (GPU) and dedicated AI accelerators. While performance and energy efficiency are essential, the reliability of these systems is equally critical. Given the time and energy requirements for training, in-field failures are extremely costly. At the same time, higher integration density and smaller feature sizes cause high chip activity and temperature. Combined with prolonged execution times, it increases the failure probabilities. This paper focuses on Electromigration (EM) issues in Static RAM (SRAM)-based register files, which act as the primary link between memory and processing cores in dataflow architectures. Our main contribution is a comprehensive EM analysis, revealing a significantly different EM profile compared to traditional SRAM-based caches. These findings highlight the cruciality of EM concern in the SRAM-based register files and open doors to new mitigation and prevention solutions.

Feature size reduction of the front End of the Line (FEoL) and back End of the Line (BEoL) elements, i.e., transistors and interconnects, has been the main enabler of the next-generation computation systems. The decreasing trend of the cross-sectional area of the interconnect in advanced technology nodes, however, comes along with a drastic increase in the resistive parasitic, substantially impacting the overall energy efficiency and performance of the computer system. Mitigation of the high parasitic resistance within an advanced-node static RAM (SRAM)-based last-level cache (LLC) is the main target of this article. To achieve this target, we augment the LLC interconnect with some degree of reconfiguration by utilizing a dynamic segmented bus (DSB). With DSB, the interconnect segments that are most actively used for a given workload can be shortened, on average, contributing to a smaller capacitive load. Hence, the efficient reconfiguration of an LLC interconnect strongly depends on the LLC demands of the application. To account for this workload dependency, we design the required microarchitectural support in an end-to-end application-to-technology flow. By optimizing the overhead of DSB switches and additional hardware modules, the SRAM-based LLC with DSB-augmented intra-macro interconnect achieves 33% energy savings and 16% reduction in total access time across eight representative workloads, with a negligible area overhead of less than 0.4%.

As technology scales down, the performance–power–area (PPA) of static random access memory (SRAM) is increasingly constrained by interconnects due to the presence of large parasitic capacitance and resistance within these structures. This article presents a co-optimization and co-design framework that integrates technology, interconnect, circuit, cache memory, and workload to optimize the overall PPA of the computing cache system through various emerging interconnect technologies under software and hardware conditions. Moreover, we present the differential transmission line (DTL), which is utilized as a hybrid with conventional wires with repeater insertion. The proposed methodology enables the identification of the optimal design, thereby facilitating the reduction of interconnect energy and delay, considering synthetic/realistic workloads and comparing DTL against traditional repeater insertion methods based on metrics of PPA, including the energy–delay–area product (EDAP) and energy–delay product (EDP), for the computing cache system. A thorough design space exploration is conducted, utilizing validated experimental subarrays at the deep scale across state-of-the-art technology nodes. Moreover, the case study assesses a range of cache system parameters, emphasizing the potential of DTL interconnect technologies to enhance cache memory PPA.

Bulk bitwise operations are commonplace in application domains such as databases, web search, cryptography, and image processing. The ever-growing volume of data and processing demands of these domains often result in high energy consumption and latency in conventional system architectures, mainly due to data movement between the processing and memory subsystems. Non-volatile memories (NVMs), such as RRAM, PCM and STT-MRAM, facilitate conducting bulk-bitwise logic operations in-memory (CIM). Efficient mapping of complex applications to these CIM-capable NVMs is non-trivial and can even lead to slowdowns. This paper presents Sherlock, a novel mapping and scheduling method for efficient execution of bulk bitwise operations in NVMs. Sherlock collaboratively optimizes for performance and energy consumption and outperforms the state-of-the-art by 10× and 4.6×, respectively.

Brain-inspired hyperdimensional computing (HDC) offers much more efficient computing compared to other classical deep learning and related machine learning algorithms. Unlike classical CMOS, emerging non-volatile memories (NVMs) used in the realization of HDC are susceptible to failures under voltage scaling, which is essential for energy saving. Although HDC is inherently robust against errors, this is only possible when hypervectors with a large dimension (e.g., 10,000 bits) are being used, resulting in significant energy consumption. This work demonstrates, for the first time, that different NVM technologies exhibit different error characteristics under voltage scaling. In contrast to conventional CMOS-based SRAM, we demonstrate that the error behavior is data-dependent and not captured by simple bit flips in emerging NVMs. We employ our cross-layer framework that starts from the underlying technology all the way up to the algorithm to develop the novel HDC training approach DropHD. DropHD considerably shrinks the size of hypervectors (e.g., from 10,000 bits down to merely 3000 bits), while maintaining a high inference accuracy. The use of aggressive voltage scaling reduces energy consumption by 1.6 x. DropHD further reduces it to up to 9.5 × while fully recovering the induced accuracy drop, i.e. without a tradeoff.

Hyperdimensional computing (HDC) has been recognized as an efficient machine learning algorithm in recent years. Robustness against noise and simple computational operations, while being limited by the memory bandwidth, make it a perfect fit for the concept of computation in memory (CiM) with emerging nonvolatile memory (NVM) technologies. For an HDC accelerator based on NVM-CiM, there are different parameters from the algorithm all the way down to the technology that interact with each other and affect the overall inference accuracy as well as the energy efficiency of the accelerator. Therefore, in this paper, we propose, for the first time, a full-stack co-optimization method and use it to design an HDC accelerator based on NVM-based content addressable memory (CAM). By incorporating the device manufacturing variability and co-optimizing the algorithm and hardware design, HDC inference on our proposed NVM-based CiM accelerator can reduce the energy consumption by 3.27x, while compared to the purely software-based implementation, the inference accuracy loss is merely 0.125%.

The Memory Wall represents a significant performance and energy bottleneck in conventional computer architecture, caused by the frequent and costly data transfers between memory and processor cores. Computation in Memory (CiM) offers a promising solution, particularly benefiting similarity computation—a key component in various computer science applications—through the use of emerging non-volatile memory (NVM) technologies. However, intrinsic non-idealities of NVM technologies coupled with noise-sensitivity of analog circuitry can impair the reliability and correct functionality of the applications. This paper performs a cross-layer technology to application reliability and performance analysis of NVM-based similarity computation in memory. We consider various NVM technologies, different CiM-based similarity computation modules, and different real-world applications that are accurately simulated in a full-system environment. The results demonstrate significant improvements in both latency (up to 12x) and energy efficiency (up to 6.7x) of NVM-CiM compared to traditional architectures. Importantly, the study finds that latency and energy are largely unaffected by the specific NVM technology used, though reliability varies significantly—up to 28% in terms of architectural vulnerability factor (AVF).

The long-term reliability of Static Random Access Memory (SRAM) is crucial for safety-critical applications, such as those in the automotive industry. In the front-end-of-line (FEoL), the transistor elements are susceptible to negative bias temperature instability (NBTI), while in the back-end-of-line (BEoL) the interconnects are susceptible to electromigration (EM), especially in scaled technology nodes. To meet safety-critical standards, it is essential to investigate the combined aging mechanisms within the SRAM array and to develop effective testing methodologies during the operational lifetime of the system. Such methodologies are also crucial for enabling the early detection of in-field failures. In this paper, a precise aging model is presented that extends the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model and includes physical modeling for EM. This approach provides insights into the combined effects of NBTI and EM on the degradation of SRAM writability, considering the entire SRAM subarray, including the bit-cell array and peripheral circuits in Fin Field-Effect Transistors (FinFET) technology.

The computation-in-memory (CiM) paradigm is widely acknowledged to tackle the memory wall problem. Additionally, leveraging non-volatile resistive memory (NVM) technologies enhances the energy efficiency of the CiM by enabling analog computation. However, the reliability of the NVM-CiM is challenged due to the inherent device and circuit imperfections, the technology-level process variation, the sensing offset, and the analog nature of the computation. In this paper, we perform comprehensive reliability analysis and mitigation from the technology all the way to the CiM application. For this aim, we accurately model the NVM device variability and imperfection and effectively model the consequent errors at the circuit level by considering crossbar parasitic and sensing offset. Subsequently, we inject these modeled faults into the CiM-enabled full-system architecture. The study quantitatively assesses the masking capability of CiM applications and explores potential mitigation techniques to enhance the overall reliability of NVM-CiM.

The long-term reliability of the Static Random Access Memory (SRAM) module, as an important component of computing architectures, is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistor elements are vulnerable to negative bias temperature instability (NBTI), while the back end of the line (BEoL) interconnect is prone to electromigration (EM). Complying with safety-critical standards as part of silicon lifecycle management (SLM) infrastructure requires an understanding of the combined aging mechanisms of transistors and interconnects in SRAM. Moreover, a precise aging model is a prerequisite for effective aging testing and mitigation strategies. For this aim, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model at the FEoL, and use measurement-calibrated physical modeling of EM at the BEoL, to create an integrated analysis that can provide deeper insights into the individual and combined effects of NBTI and EM for SRAM operation. Our findings reveal the mutual acceleration of delay faults and hard stuck-at faults caused by NBTI and EM in SRAM, offering a precise methodology for estimating the time to failure under these conditions.

Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

The computation-in nonvolatile memory (NVM-CiM) approach addresses the growing computational demands and the memory-wall problem faced by traditional processor-centric architectures. Computation-in-memory (CiM) capitalizes on the parallel nature of memory arrays enabling effective computation through multirow memristor reading and sensing. In this context, the conventional design of memory decoders needs to be accordingly modified for efficient multirow activation and parallel data processing. This article presents the design and optimization of address decoders for NVM-CiM system architectures, employing a cross-layer co-optimization approach that integrates circuit and architecture design with application requirements. Our methodology starts at the circuit level, examining various decoder designs, including cascaded, hierarchical, latched, and hybrid models. An in-depth application-level characterization follows, utilizing an extended NVM-CiM-capable gem5 simulator to assess the impact of these decoders on the mapping of CiM-friendly applications and the resulting system performance, particularly in facilitating rapid and efficient activation of multirow memory configurations. This holistic analysis allows us to identify the bottlenecks and requirements from the application side and adjust the design of the decoder accordingly. Our analysis reveals that Hybrid Decoders significantly decrease latency and power consumption compared to other decoder designs within NVM-CiM systems. This highlights the crucial role of the decoder’s row selection flexibility, reducing additional system-level data movement even at the expense of its performance, can substantially improve the overall efficiency of NVM-CiM systems.

SRAM performance is highly dominated by interconnects as technology scales down because of the significant parasitic resistance and capacitance in the interconnect. This paper introduces a framework for the co-design of technology, interconnect, and cache memory with tag array overhead, to optimize the performance of cache memory using a variety of emerging interconnect technologies. In addition, we introduce an innovative E-Tree interconnect aimed at further decreasing the average interconnect length with the consideration of realistic workloads and benchmark against its traditional H-Tree counterparts in terms of various performance metrics, such as energy-delay-area product (EDAP) or energy-delay product (EDP) in the SRAM cache memory system. A comprehensive investigation of design space is conducted, employing realistic, deeply scaled subarray designs across a range of cutting-edge technology nodes. Furthermore, the case study examines various cache memory system design parameters to assess the true potential of emerging interconnect technologies in achieving optimal performance at the cache memory system.

This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for machine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in-memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technologies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in resistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to reliability and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory layouts and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications.

Static RAM (SRAM) is one of the critical components in advanced VLSI systems whose performance, capacity, and reliability have a decisive impact on the entire system. It offers the fastest memory in the storage hierarchy of modern computer systems. By moving toward the smaller CMOS technology nodes, the back end of the line (BEoL) interconnects are also fabricated in tighter pitch size. Hence, besides the power lines, SRAM word- and bit-line (WL and BL) are also susceptible to electromigration (EM). Therefore, EM reliability of SRAM's WL and BL needs to be analyzed during design technology co-optimization (DTCO) cycle. In this work, we investigate the impact of technology scaling on SRAM designs and perform a detailed analysis on the trend of their EM reliability and energy consumption. Our analysis shows that although scaling down the CMOS technology can result in a 2.68x improvement in the energy efficiency of the SRAM module, it increases the EM-induced hydrostatic stress by 2.53x.

The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead.

To overcome the bottleneck of the classical processor-centric architectures, Computation-in-Memory (CiM) is a promising paradigm where operations are performed directly in memory. Recent works propose the use of CiM to accelerate neural networks or hyperdimensional computing, but also for memory encryption solutions. As CiM facilitates the computation in the analog domain and the output is driven through current sensing, CiM could potentially be highly vulnerable to power side-channel attacks. In this work, we analyze the vulnerability for power side-channel attacks in various CiM implementations based on Static Random Access Memory (SRAM) and emerging nonvolatile memristive technologies. Our results show that a side-channel attacker can recover secret data used in an XOR operation with only a few hundred measurements, where CiM architectures based on emerging memristive technologies are more vulnerable than SRAM-based CiM. Therefore, we propose two different types of countermeasures based on hiding and masking, which are tailored to CiM architectures. The efficiency of our proposed countermeasures is shown by both attacks and leakage assessment methodologies using one million measurement traces.

For on-chip SRAM, a major portion of delay and energy is contributed by the H-Tree interconnects. In this paper, we propose an E-Tree interconnect technology to minimize the H-Tree delay and energy overheads based on an efficient interconnect technology/memory co-design framework for nonuniform workloads. Various array- and interconnect-level design parameters are co-designed for optimal performance using three emerging interconnect materials with a realistic cell library.

The matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning hardware accelerators. The crossbar array structure with memristive devices as a building block has an inherent capability to perform energy-efficient MVM. However, the memristive devices suffer from various non-idealities as well as limited number of stable levels. Therefore, the reliability and in turn inference accuracy of the deep learning application is negatively impacted. Thus, this paper presents a low overhead checksum-based error correction method for memristive crossbars for MVM computation. The proposed methodology alleviates the problem of storing the checksum value into multiple columns of the crossbar due to the limited number of stable levels of memristive devices. The number of extra columns required for storing the checksum value is reduced, resulting in a significant reduction in the memory overhead by up to 75%. The proposed method scales the checksum value of trained neural networks (NNs) and then performs checksum-aware retraining, and results show negligible impact (∼3%) on the inference accuracy of the NNs on MNIST, Fashion-MNIST, CIFAR-10, and Veg-15 datasets.

Memory cells in emerging non-volatile resistive memories often have asymmetric switching properties, where reliable write operations are achieved by setting the write period to a fixed value. To improve their performance and energy efficiency, self-terminating write schemes have been proposed, in which the write signal is stopped after the required state change has been observed. In this work, we show how this data-dependent write latency can be exploited as a side-channel in multiple ways to unveil restricted memory content. Moreover, we discuss and evaluate potential approaches to address the issue.

Analog Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency. Spin-Transfer Torque Magnetic Memory (STT-MRAM) is one of the promising technologies for CiM architectures. Although STT-MRAM has various benefits, it does not have the potential to be used directly in analog multi-value CiM operations due to its limited levels of cell resistance states. In this paper, we propose a novel flexible multi-value design for STT-MRAM (MVSTT) with the potential to be used for multi-value CiM. In the multi-value CiM, we are able to have various 2sresistive state combinations from$s$selected MTJs, which is not possible in the normal STT-MRAM CiM. The size of the MVSTT can be adjusted at run-time depending on the application's requirements. The benefits of the proposed scheme are quantified in representative applications such as multi-value matrix multiplications, which is the basic computation of Neural Networks applications. For the multi-value matrix multiplication, the energy, and delay gain is up to 9.7 × and 13.3 ×, respectively, to non-CiM matrix-vector-multiplication. Also, for the neural network, the proposed design allows up to a 32 × reduction in the STT-MRAM cells per crossbar to achieve a similar inference accuracy as the binarized neural network.

Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.

Matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning and big data applications. On the other hand, the Memory wall problem in traditional processor-centric architectures limits the performance of these applications. The crossbar array of emerging non-volatile memristive devices (memristive crossbar) provides an energy-efficient hardware implementation of MVM for deep learning accelerators and edge computing hardware. However, non-idealities as well as manufacturing and runtime defects of the memristive devices may severely impact the reliability of target applications. This paper presents a new online block error correction technique for memristive crossbars. It enables reliable MVM computation by combining the idea of checksum and Hamming code-based linear coding scheme. The proposed method can correct any number of errors in one particular array block containing multiple columns. An adaptive error correction coding strategy is also presented, so that the ratio of data columns to the parity checksum columns can be adjusted at runtime based on the fault rate, enabling the optimum use of data and parity checksum columns.

Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency, which is a promising approach to address so-called memory wall of conventional von Neumann architectures. Redox-based Random access memory (ReRAM) is an appropriate candidate for the realization of CiM concepts in CMOS co-integrated crossbar structures. However, ReRAM devices suffer from inherent variability in fabrication and operation. In this paper, we propose a statistical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on this, a comprehensive reliability analysis is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture has a high failure probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

Moving to more advanced CMOS technologies can improve the performance and energy efficiency of the VLSI systems, including the static RAM (SRAM) as one of the most demanding memory elements of the modern computer systems. However, the long-term reliability of the SRAM is also important and needs to be carefully considered. This is particularly of utmost importance in safety critical systems, including automotive, with stringent requirements for in-field testing. In advanced technology nodes, the interconnects are designed in a tighter pitch-size, which result in an increase in the current density. Moreover, due to the higher chip complexity, the operating temperature is typically higher. Both the high current density and high temperature exacerbate the electromigration (EM) phenomenon in interconnects, which eventually leads to resistance increase and timing faults. This negatively influences the long-term reliability of the system. Because of the EM, SRAM-based memory modules may undergo field failure, such as read or write faults. To avoid functional safety violation, early detection and prediction of the EM is crucial. In this work, we propose an optimized EM test methodology which is able to predict the effect of EM up to 9.7 months earlier before it leads to failures in normal functional mode.

Performing the computation in memory (CiM) based on the resistive non-volatile memories can significantly improve the energy efficiency and performance of data-intensive and deep learning applications. Activating multiple rows of the memories at the same time is required in Multiply and Accumulation (MAC) operation of neural networks. This simultaneous activation, however, increases the current density of the shared interconnect, which exacerbates the Electromigration (EM) risk. This paper analyzes the EM phenomenon in CiM-oriented MAC paradigms based on emerging non-volatile resistive memories including Spin Transfer Torque Magnetic RAM (STT-MRAM), Redox-based RAM (ReRAM), and Phase Change Memory (PCM). We show how EM is exacerbated compared to normal memory architectures. For EM analysis in CiM, we modify the existing EM models, and consider different interconnect and array dimensions. We also propose the EM-aware row activation pattern as effective means to mitigate the EM degradations in the analog MAC paradigms.

Emerging non-volatile memories facilitate the Computation in Memory (CiM) paradigm. Performing operations with the concept of CiM plays a crucial role in the efficiency improvement of data-intensive applications. Resistive switching RAM (ReRAM) and Spin Transfer Torque Magnetic RAM (STT-MRAM) are promising candidates for the CiM implementation. Reliable CiM implementation with these resistive non-volatile memories (memristive devices) is challenging and error-prone since the manufacturing process of both the memristive components and the CMOS components are susceptible to the temperature- and voltage-dependent variation. Moreover, the small distance between the distinct resistive levels of the STT-MRAM, and time-dependent resistance drift in ReRAM, exacerbates the reliability of CiM implementations. In this paper, we perform a detailed study on the impact of the temperature and voltage biasing on the variation in both the STT-MRAM and ReRAM technologies as well as propose a voltage tuning scheme to significantly improve the sensing reliability of CiM implementations based on these technologies. We also investigate the impact of our proposed voltage tuning scheme on the power consumption and performance of the CiM circuitry.

Conventional von Neumann architectures cannot successfully meet the demands of emerging computation and data-intensive applications. These shortcomings can be improved by embracing new architectural paradigms using emerging technologies. In particular, Computation-In-Memory (CiM) using emerging technologies such as Resistive Random Access Memory (ReRAM) is a promising approach to meet the computational demands of data-intensive applications such as neural networks and database queries. In CiM, computation is done in an analog manner; digitization of the results is costly in several aspects, such as area, energy, and performance, which hinders the potential of CiM. In this article, we propose an efficient Voltage-Controlled-Oscillator (VCO)–based analog-to-digital converter (ADC) design to improve the performance and energy efficiency of the CiM architecture. Due to its efficiency, the proposed ADC can be assigned in a per-column manner instead of sharing one ADC among multiple columns. This will boost the parallel execution and overall efficiency of the CiM crossbar array. The proposed ADC is evaluated using a Multiplication and Accumulation (MAC) operation implemented in ReRAM-based CiM crossbar arrays. Simulations results show that our proposed ADC can distinguish up to 32 levels within 10 ns while consuming less than 5.2 pJ of energy. In addition, our proposed ADC can tolerate ≈30% variability with a negligible impact on the performance of the ADC.

Electromigration (EM) has been known as a reliability threatening factor for back-end-of-the-line interconnects. Spin-transfer torque magnetic RAM (STT-MRAM) is an emerging nonvolatile memory that has gained a lot of attention in recent years. However, relatively large operational current magnitude is a challenge for this technology, and hence, EM can be a potential reliability concern, even for the signal lines of this memory. A workload-aware EM modeling needs to capture time-dependent current density in the memory signal lines and to be able to predict the effect of the EM phenomenon on the interconnect for its entire lifetime. In this work, we present methods to effectively model the workload-dependent EM-induced meantime to failure (MTTF) in typical STT-MRAM arrays under a variety of realistic workloads. This allows performing the design-space exploration to co-optimize reliability and other design metrics.

Computation in Memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the implementation of CiM architectures. However, the much smaller off/on ratio of resistance states compared to other non-volatile memories makes CiM implementation challenging in this technology. This is further exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction (MTJs) and CMOS components, resulting in erroneous CiM operations. In this paper, we perform a detailed technology-aware statistical failure analysis of CiM operation and design the optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations. Our results show that using a simpler model of CiM array is sufficient for the optimization of the sensing circuitry. However, it may lead to over-optimistic estimation of failure rates. Therefore, a more comprehensive model is utilized for accurate estimation of CiM failure rates.