A selective harmonic elimination pulse width modulation (SHEPWM) class-D amplifier (CDA) with a reconfigurable gate driver integrated circuit (IC) is proposed. The H-bridge CDA generates a three-level SHEPWM signal and cancels lower order harmonics of the switching voltage. To generate accurate pulses at the right switching angles, GaN devices are used and a reconfigurable gate driver IC is used to control the driving strength of the gate driver. The SHEPWM algorithm is implemented in an FPGA and can configure the output on-the-fly. The simulation results show that the SHEPWM CDA has a 0.48 % total harmonic distortion (THD) for a 10 kHz output with an estimated switching loss of 38 mW for a GaN power transistor. It also shows that the driving strength of the gate driver has very little effect on THD, therefore the driving strength can be optimized between overshoot voltage and switching loss without concern for THD.

This paper presents a new dual-inductor hybrid boost converter (DI-HBOC) with two inductors located at the output. This structure allows continuous current delivered to the load, thus, reducing the output filtering capacitor size and the output voltage ripple. By relocating the inductor at the output, which is the lower current path, the conduction loss on the inductor can be significantly reduced. The right half plane zero (RHPZ) in the control-to-output transfer function can also be eliminated; therefore, a simple pulse-width modulation (PWM) voltage-mode controller can be used for the proposed DI-HBOC while still achieving high closed-loop bandwidth and fast transient response. The distinct features of the proposed converter are analytically demonstrated. A 12-to 24 V DI-HBOC and a conventional BOC (CBOC) using low-ÆoN GaN switches with PWM voltage-mode controller are also implemented in PSIM for verification and comparison. The simulated peak power efficiency is 97.4 % that is 1.17 % higher than the CBOC. At 3 A load current, the power efficiency is improved by 9.7 % and the output ripple is only 17.5 mV, 6x lower than in CBOC.

This paper presents a novel and compact bandgap comparator (BGRCOMP) for under-voltage lockout (UVLO) and thermal shutdown (TSD) protection circuits. The proposed BGRCOMP is self-referenced and combines the advantages of both a high-accuracy bandgap reference and a comparator into one single circuit. A latch-controlled biasing technique is also presented, which reduces static power consumption of the proposed BGRCOMP. The proposed BGRCOMP is used for the design of compact and low power UVLO and TSD circuits. The post-layout simulation results using a 0.18 μm BCD-on-SOI technology prove the attractive performance of the UVLO and TSD with a static current (Iq) of 7.76 μA and 5.4 μA from a 5 V supply, respectively. The deviations of UVLO thresholds are less than 3 mV in the temperature range of -40~85 °C.

This paper presents a compact configurable power control system for safety-critical applications, which operates in harsh environments. This heterogeneous integrated mixed digital, analog and high-voltage design for power applications is implemented in a system-in-package (SiP) module using a low-temperature co-fired ceramics (LTCC) substrate. A comparison between technologies for SiP designs shows that LTCC is advantageous in terms of integration density, thermal and electrical performances, as well as signal and power integrity. In addition, this work proposes layout and fabrication techniques for the enhancement of thermal, electrical performances and integration density specific to LTCC-based designs, such as chip-covering, multi-layer routing of power signals and self-damped transmission lines. An improvement of 59% in available area, 32% reduction of temperature due to self-heating, 65% loss reduction and 22% reduction in interference coupling were obtained when compared to a baseline design.