This article presents a power-efficient echo-cancellation-based hybrid architecture for full-duplex (FD) chip-to-chip interconnects. Conventional FD transceivers employ three separate transconductance stages for signal transmission, replica generation, and signal separation, thereby increasing overall power consumption (PC). The proposed hybrid topology reduces this overhead by integrating a linear resistor within the replica driver (RD) for retrieving the incoming signal from the tri-level superimposed signal at the transceiver interface. This makes the proposed hybrid power-efficient compared to the existing FD hybrid circuit topologies. The prototype design has been fabricated in 1.2-V, 65-nm CMOS technology. The measured results of the proposed hybrid circuit have a received signal with an eye-opening of 20 mV at a data rate of 8 Gb/s over a 20-cm FR4 PCB trace. The proposed hybrid achieves a PC of only 0.3mW and an energy efficiency of 0.075 pJ/bit. The active silicon area occupied by the hybrid is$0.0045~\mathrm {mm}^{2}$.

This paper presents an energy-efficient, half-rate charge-steering logic (HR-CSL) based echo cancellation hybrid (ECH) circuit topology for full-duplex(FD) signaling across chip-to-chip interconnects. The proposed charge-steering logic (CSL) based hybrid has much lower power consumption compared to conventional current-mode logic (CML) and voltage-mode logic (VML) based hybrid implementations, thanks to the discrete nature of CSL hybrid topology avoiding direct current path between$V_{DD}$and ground. The prototype test chip design of the proposed hybrid circuit topology has been fabricated in 65 nm CMOS for a 20 cm FR4 PCB chip-to-chip interconnect with a supply voltage of 1.2 V. The measurement performance of the HR-CSL based hybrid circuit achieves 8 Gb/s FD operation at a power consumption of only 0.15 mW with an energy efficiency of 0.0375 pJ/bit. The measurement results show that the proposed hybrid circuit has a differential received signal voltage swing of 110 mV at 8 Gb/s data rate with a timing jitter of 20 ps. The proposed hybrid has a clock phase margin of 25% UI at bit-error-rate (BER) less than$10^{-12}$. The active area of the hybrid is 0.0007 mm2.

The conventional power-hungry current and voltage-mode hybrid circuit topologies are not suitable for full-duplex(FD) front-end receivers, and they are not directly compatible with modern digital signal processing (DSP) cores as they suffer from low output differential eye-opening at high data rates. Moreover, they require extensive equalization and post-amplifier circuits to improve the eye-opening of the received signal at the cost of an additional power penalty and the increased circuit complexity. As a result, the overall energy-efficiency of the transceiver circuit becomes poor. To address this issue, in this work, the authors propose a half-rate StrongArm latch comparator based hybrid(HR-SALCH) for FD signaling over off-chip interconnect. The StrongArm latch comparator(SALC) circuit topology has the advantages of rail-to-rail voltage swing, digital equalization, and low static power dissipation and hence it is suitable candidate for realizing an energy-efficient receiver front-end hybrid circuit in FD off-chip communication. The proposed StrongArm latch comparator based hybrid(SALCH) is designed in 1.2 V, 65 nm CMOS at 6-Gb/s FD data rate over FR4-PCB interconnect of length 20 cm. The post-layout simulation results show that the proposed full-duplex transceiver deploying SALCH circuit topology has rail-to-rail output voltage swing with the timing jitter of 11 ps. The power consumption of the SALCH circuit topology is only 0.62 mW with an energy efficiency of 0.2 pJ/b at 6-Gb/s full-duplex operation.

The conventional current-mode pseudo-random bit sequence (PRBS) generators suffer from high-power consumption, low output voltage swing and they are not directly compatible with the CMOS static logic circuit. To address this issue, this work proposes power-efficient, 27-1, 20-Gb/s, half-rate pseudo-random bit sequence(HR-PRBS) generators by employing current-integrating latch circuit topology using incomplete settling at 20-Gb/s data rate implemented in 1.2 V, 65 nm CMOS. The proposed current-integrating logic latch based PRBS implementations achieves low power consumption, high speed and high voltage swing thanks to incomplete settling behaviour of the CIL circuit topology. The proposed PRBS generator implementations employing current-integrating latch topology consumes power of 0.76-mW/Gb/s while operating at 20-Gb/s data rate. The differential eye-opening of the proposed current-integrating logic (CIL) HR-PRBS generator is 1.6 V at 20-Gb/s date rate.

This work proposes a 27-1, low power, half-rate, StrongArm latch based pseudo-random bit sequence (SAL-PRBS) generator at a 15-Gb/s data rate. The proposed SAL-PRBS consumes low static-power consumption compared to current-mode logic (CML) based PRBS circuit topologies, thanks to the StrongArm latch (SAL) comparator circuit topology having virtually zero static power consumption. The proposed design is implemented in 1.2 V, 65 nm CMOS. The simulation results show that the SAL-PRBS consumes only 3.7 mW at a 15-Gb/s data rate. The output data sequence of SAL-PRBS has rail-to-rail output voltage signal swing with a timing jitter of 2 ps. The figure-of-merit(FoM) of the proposed SAL-PRBS generator is only 0.036-pJ/bit at a 15-Gb/s data rate.

In this paper, an energy efficient current-mode hybrid circuit topology for echo-cancellation is proposed for full-duplex signalling over chip-to-chip interconnects. Conventional full-duplex transceivers consists of three transcondutors, namely, for transmitting the outbound signal, for replica generation and for cancellation or subtraction, leading to an increase in the power consumption. However, the proposed hybrid circuit topology consists of only two transconductors, transmitter and replica generator. The separation of the inbound signal from the signal on the line is achieved using a simple resistor, thereby eliminating the need of additional transconductor for subtraction. This makes the proposed hybrid an attractive choice for realizing power efficient full-duplex transceiver compared to the existing transceiver with current-mode and voltage-mode hybrid circuit topologies. The proposed hybrid is implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout simulation including the package parasitic has a differential received signal voltage swing of 85 mV at 10 Gb/s data rate over a 20-cm FR4 PCB trace. The total power consumption of the hybrid is 0.29 mW and the corresponding energy efficiency is 0.057 pJ/bit. The layout of the hybrid occupies an area of 0.00025 mm2.

In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between VDDand ground. The half-rate hybrid circuit topology has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout performance of the half-rate charge-steering hybrid including package parasitic has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a FR4 PCB interconnect of length 20 cm. The total power consumption of the half-rate charge-steering hybrid is only 0.16 mW and its energy efficiency is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm2.

Full-duplex communication over on-chip interconnects requires a hybrid circuit that separates the inbound signal from the superimposed signal by subtracting the outbound signal. This operation results in an echo and incomplete cancellation of this echo leads to residue. Non-zero residue reduces the amplitude and timing margins in the recovered signal eye-diagram. This work for the very first time proposes an adaptive transceiver for near zero-residue for full-duplex communication over on-chip interconnects by deploying a residue monitor. The proposed hybrid circuit topology employs low power charge-mode integrated circuits compared to traditional high power consuming current-mode and voltage-mode echo-cancellation circuits. In the proposed scheme, the operation of cancelling the outbound signal is assisted by a replica generation stage which replicates the outbound signal in terms of signal swing is realized by the digitally re-configurable capacitor-bank. The echo-cancellation is implemented at the circuit level in 1.2V, 65 nm CMOS over a 1-mm on-chip interconnect and the residue monitor architecture is realized with behavioural modeling in Verilog-AMS. The proposed scheme operates at a data rate of 10-Gb/s with a total power consumption of 9.64 mW. The loop locks for a control voltage of 173 mV with an adaptation time of 5.74 ns and the corresponding swing of the replica signal is 230.13 mV with a final residue of only 3.13 mV. The extracted inbound signal has a differential swing of 154 mV.