This paper presents an extremely low-voltage flip-flop (ELVFF) consisting of recursive stacking body-bias logic gates with the capability of operating at extremely low supply voltages. The ELVFF is based on a conventional NAND latch based flip-flop (NLFF), and consists of three-times-recursive-stacking body-bias NANDs (3RSBB-NANDs) and onetime-recursive-stacking body-bias inverters (1RSBB-INVs). The recursive-stacking and body-bias techniques provide an effective strategy for achieving ELV operation. The combination of these techniques allows for the enhancement of both the voltage gain and voltage swing of logic gates, thereby enabling the ELVFF to operate at extremely low supply voltages. Simulation results in a standard 180-nm CMOS process with a deep-n-well option indicated that our proposed ELVFF was capable of operating at an extremely low supply voltage of 40 mV. Measurement results also demonstrated that the ELVFF stored and maintained the correct logic with an amplitude of 27 mV and a power dissipation of 6.03 nW at a 39-mV power supply. The ELVFF is suitable for sub-100-mV ELV applications, such as energy harvesting, at the cost of an increased number of transistors, area, power, and delay time.

This paper presents a programmable differential bandgap reference (DBGR) for ultra-low-power IoT (Internet-of-Things) edge node devices. The circuit consists of a bandgap reference (BGR) based current generator (CG) and differential voltage generator (DVG). The BGR-based CG generates a current and a voltage, and the DVG generates another voltage from the current. A differential voltage reference can be obtained by taking the voltage difference from the voltages. The circuit can produce a programmable output differential voltage by changing the multipliers of MOSFETs in a differential pair and resistance with digital codes. Simulation results demonstrate that the proposed DBGR can generate a 25- to 200-mV reference voltage with a 25-mV step within a ±0.7% temperature inaccuracy in a range from −20 to 100°C. The power was 87 nW. A Monte Carlo simulation showed that the coefficient of the variation in the reference was within 1.1%.

Low-voltage charge pump (CP) and its dedicated multi-stage driver (DRV) for sub-50-mV energy harvesting are proposed. The proposed DRV utilizes the output voltages of each CP to efficiently boost the control clock signals. The boosted clock signals are used as switching signals for each CP and DRV to turn switch transistors on and off. Moreover, reset transistors are added to the DRV to ensure an adequate non-overlapping period between switching signals. Simulated results demonstrated that (i) the proposed DRV can generate boosted clock signals of 712.6 mV from input voltage of 100 mV and (ii) the multi-stage CP can generate output voltage of 702.5-mV. Peak efficiency of the CP is 42.9%. The proposed CP and DRV can operate at extremely low voltage of 41 mV.