The Design of efficient, safe, and reliable circuits is a prime objective in high-voltage (HV) electronic systems, such as switched-mode power amplifiers (PAs). One of the main causes of efficiency degradation and reliability problems, in these amplifiers, is the shoot-through current from the HV power supply to the ground. To eliminate such current, a dead time generator (DTG) is used to modify the signals propagating through the high-side and low-side gate drivers by adding a fixed dead time between them. However, any delay mismatch between these gate drivers can reduce the dead time to the point that it becomes negative. In this paper, an HV-DTG architecture is introduced. The architecture mitigates the effects of delay mismatch variations in gate drivers, which can result from parameters mismatch, fabrication process variations, and temperature variations. An HV switched-mode class-D power amplifier is used to illustrate the performance of the DTG. The amplifier is implemented in a low-cost$0.35~\mu m$HV CMOS process. The total area of the PA is$0.5~mm^{2}$, where the DTG covers an area of$0.066~mm^{2}$. A measured system’s efficiency of 95.14% is achieved with the shortest dead time of 10.8 ns, which is 1.38x smaller than the generated dead time in comparable state-of-the-art HV dead time generators.

This paper proposes a methodology based on machine learning to find apparent causal relations between performance targets and design variables in analog circuits. Diversified filtering and wrapping variable selection algorithms are utilized to construct a causal graph that identifies the major circuit design parameters that can be used to optimize the performance of analog circuits. Based on the constructed causal graph, a sequence of design procedures can be extracted and followed to optimize the performance of a design. The proposed methodology is validated using a two-stage op-amp. The obtained causal graph agrees with analytical design equations published in the literature for the selected two-stage op-amp. The results also show that the proposed methodology can accelerate the circuit design process and effectively help designers understand the reasoning behind different design decisions.

This paper presents the design and analysis of combining input-voltage feedforward and proportional-integral (PI) controllers to regulate the output voltage of DC-DC Buck converter subject to input line disturbances. Non-idealities of the Buck converter such as passive and active components parasitics are included in the mathematical model obtained by the statespace averaging (SSA) technique for accurate control. The stability boundary locus approach is used to graphically analyze the system stability. It guides the design of the PI controller gains and the feedforward scaling factor to achieve desired phase and gain margins. Analysis shows that the feedforward scaling factor affects the stability regions of the closed-loop system and can limit the possible PI controller gains for certain phase and gain margins; 75oand 9.54 dB in our case. The results are verified by a Simulink model developed for the Buck converter system.

In this paper, we propose a novel design methodology for a deadtime generator for high-efficiency power amplifiers. It consists of a two-phase non-overlapping clock circuit and level down shifters. A 3% improvement in efficiency is achieved with a maximum efficiency of 94% in a class-D power amplifier circuit. The proposed design generates a deadtime as low as 16.7ns and eliminates the problem of propagation delay mismatch between high side and low side gate drivers. The circuit is implemented in 50V AMS 0.35 μm CMOS technology. The deadtime generator consumes 16.5 mW, while occupying a total area of 0.068 mm2.