This paper presents a sub-harmonic injection-locked sub-sampling PLL (SIL-SSPLL) that realizes a peaking-free jitter transfer. The use of an injection-locked oscillator (ILO) in SSPLL allows the PLL open-loop transfer function to achieve a higher phase margin, thereby enhancing the jitter performance. The study also analyzes the effects of injection locking strength on noise rejection for both the reference signal and the VCO showing that optimal jitter performance can be achieved by properly setting the injection strength. A 13.6 to 17.7 GHz SIL-SSPLL prototype fabricated in a 40 nm CMOS technology demonstrates 74 fs RMS integrated jitter at 15.8 GHz while consuming 22.6 mW of power, leading to an excellent figure of merit (FoM) of -249.1 dBc/Hz.

This paper proposed a cascaded harmonic enhanced injection-locked frequency tripler fabricated in a 40-nm CMOS process. In order to suppress the fundamental signal and the second harmonic signal, an injection-locked doubler is explored, and then the obtained ×2 frequency signal is mixed with the fundamental signal to realize the third harmonic signal and then the third harmonic signal is injected into the tank of the injection-locked frequency selection network to improve the output power. The tripler achieves a fundamental suppression over -69 dBc and a second harmonic suppression over -66 dBc. The output power over the entire locking range from 71.5 to 86.7 GHz is larger than 5.5 dBm. The chip occupies a die area of 0.25 × 0.35mm2and dissipates 20 mW of power.

This paper presents a continuous frequency switching zig-zag voltage-controlled oscillator (VCO) to overcome the frequency discontinuity problem during the band switching process in multi-band wideband VCOs. Complementary PMOS and NMOS varactors are explored to realize opposite VCO tuning gains with high linearity. The VCO reduces the nonlinearity of the transmitted chirp in frequency-modulated continuous-wave (FMCW) radars, improving the range resolution. Implemented in a 40-nm CMOS technology, the proposed zig-zag multi-band VCO shows a simulated maximum peak frequency error of 10 MHz over 23.4-27.6 GHz frequency range, a −106.6 dBc/Hz phase noise at 1 MHz offset, and a −183.1 dBc/Hz FoM while consuming 12.69 mW power.