This paper proposes a deep learning model (RCNet) for Delta-Sigma (ΔΣ) ADCs. Recurrent Neural Networks (RNNs) allow to describe both modulators and filters. This analogy is applied to Incremental ADCs (IADC). High-end optimizers combined with full-custom losses are used to define additional hardware design constraints: quantized weights, signal saturation, temporal noise injection, devices area, capacitor mismatch, and finite-gain amplifier. Focusing on DC conversion, our early results demonstrate thatSNRdefined as an Effective Number Of Bits (ENOB) can be optimized under a certain hardware mapping complexity. The proposed RCNet succeeded to provide design tradeoffs in terms ofSNR(>13bit) versus area constraints (OSR(80 samples). Interestingly, it appears that the best RCNet architectures do not necessarily rely on high-order modulators, leveraging additional topology exploration degrees of freedom.

This paper presents J3DAI, a tiny deep neural network-based hardware accelerator for a 3-layer 3D-stacked CMOS image sensor featuring an artificial intelligence (AI) chip integrating a Deep Neural Network (DNN)-based accelerator. The DNN accelerator is designed to efficiently perform neural network tasks such as image classification and segmentation. This paper focuses on the digital system of J3DAI, highlighting its Performance-Power-Area (PPA) characteristics and showcasing advanced edge AI capabilities on a CMOS image sensor.To support hardware, we utilized the Aidge comprehensive software framework, which enables the programming of both the host processor and the DNN accelerator. Aidge supports post-training quantization, significantly reducing memory footprint and computational complexity, making it crucial for deploying models on resource-constrained hardware like J3DAI.Our experimental results demonstrate the versatility and efficiency of this innovative design in the field of edge AI, showcasing its potential to handle both simple and computationally intensive tasks.

With the escalating concern about global warming, the environmental impact of electronic devices must be scru-tinized. Life Cycle Assessments (LCA) reveal that Integrated Circuits (ICs) are the primary contributors to greenhouse gas emissions in these devices. However, performing an inventory to determine the ICs impact is a complex task due to missing data and the existing studies on ICs have been neglecting CMOS Image Sensors (CIS). Despite the surge in CIS usage, particularly in smartphones, there is a lack of comprehensive models to assess their en-vironmental impact. This paper proposes a multi-level set of models that leverage available information while considering the specificities of CIS. The most comprehensive model incorporates factors such as the total silicon area, geographical location (influencing the energy mix), and the technology node. To accommodate scenarios with incomplete data, subsequent models are designed to effectively utilize averaged parameters. The proposed models are applied to sensors manufactured by STMicroelectronics and Sony, and the results are compared with existing LCA results from Fairphone. Our approach provides a more comprehensive understanding of the environmental impact of CIS, contributing to the broader goal of reducing the carbon footprint of electronic devices. Our results suggest that the carbon impact of a Fairphone 4 image sensor is likely higher than previously estimated, with a significant gap between our findings and the expected value.