In this paper, we investigate the single event effects under proton irradiation for the state-of-the-art embedded GPU NVIDIA Jetson Orin NX System-on-Module (SoM). Designed for deployment across safety critical domains and in particularly automotive, this system represents a cutting-edge advancement in high performance embedded computing with functional safety features, which makes it an ideal candidate for use in space systems. Our study evaluates the Single-Event Effects (SEE) manifested within the SoM’s central processing unit (CPU), graphics processing unit (GPU), and associated peripherals. Through our analysis, we aim to delineate the origins of Single Event Functional Interrupts (SEFI) occurring at the SoM level. Furthermore, we provide a detailed exposition on the errors observed within the GPU complex, elucidating the requisite conditions for their manifestation. Unlike previous works which treat embedded GPUs under irradiation as black box, we are able to identify the source of SEEs through ARM’s RAS subsystem, and observe for the first time in literature GPU SEEs. Our investigation culminates in a comprehensive assessment of the SoM’s susceptibility, identifying particularly sensitive components.

Microprocessor power consumption and dependability are both crucial challenges that designers have to cope with due to shrinking feature sizes and increasing transistor counts in a single chip. These two challenges are mutually destructive: microprocessor reliability deteriorates at lower supply voltages that save power. An important dependability metric for microprocessors is their radiation-induced soft error rate (SER). This work goes beyond state-of-the-art by assessing the trade-offs between voltage scaling and soft error rate (SER) on a microprocessor system executing workloads on real hardware and a full software stack setup. We analyze data from accelerated neutron radiation testing for nominal and reduced microprocessor operating voltages. We perform our experiments on a 64-bit Armv8 multicore microprocessor built on 28 nm process technology. We show that the SER of SRAM arrays can increase up to 40.4% when the device operates at reduced supply voltage levels. To put our findings into context, we also estimate the radiation-induced Failures in Time (FIT) rate of various workloads for all the studied voltage levels. Our results show that the total and the Silent Data Corruptions (SDC) FIT of the microprocessor operating at voltage-scaled conditions can be 6.6 × and 16 × larger than at the nominal voltage, respectively. Moreover, changes in the microprocessor’s clock frequency do not have a noticeable impact on its soft error susceptibility. The findings of this work can aid computer architects in striking a balance between power and dependability, thus, designing more robust and efficient microprocessors.