Encrypted traffic classification has become a crucial task for network management and security with the widespread adoption of encrypted protocols across the Internet and the Internet of Things. However, existing methods often rely on discrete representations and complex models, which leads to incomplete feature extraction, limited fine-grained classification accuracy, and high computational costs. To this end, we propose TrafficAudio, a novel encrypted traffic classification method based on audio representation. TrafficAudio comprises three modules: audio representation generation (ARG), audio feature extraction (AFE), and spatiotemporal traffic classification (STC). Specifically, the ARG module first represents raw network traffic as audio to preserve temporal continuity of traffic. Then, the audio is processed by the AFE module to compute low-dimensional Mel-frequency cepstral coefficients (MFCC), encoding both temporal and spectral characteristics. Finally, spatiotemporal features are extracted from MFCC through a parallel architecture of one-dimensional convolutional neural network and bidirectional gated recurrent unit layers, enabling fine-grained traffic classification. Experiments on five public datasets across six classification tasks demonstrate that TrafficAudio consistently outperforms ten state-of-the-art baselines, achieving accuracies of 99.74%, 98.40%, 99.76%, 99.25%, 99.77%, and 99.74%. Furthermore, TrafficAudio significantly reduces computational complexity, achieving reductions of 86.88% in floating-point operations and 43.15% of model parameters over the best-performing baseline.

The widespread deployment of Internet of Things (IoT) devices has made them vulnerable targets for cyber attacks, highlighting the great significance of IoT device identification for network security management. Existing studies have primarily focused on either manual extraction of excessive network traffic features or heavy reliance on labeled data. To address these limitations, we propose a novel IoT device identification approach (named IoT-SCNet) via semi-supervised contrastive learning of network traffic visual representations. Specifically, IoT-SCNet converts two packet-level features and raw traffic into network traffic images of each device, and applies three augmentation strategies designed for network traffic to construct semantically meaningful positive/negative image pairs. By deep neural networks automatically capturing discriminative patterns and a contrastive task, IoT-SCNet achieves effective identification of diverse IoT device types. Comprehensive evaluations across three benchmark datasets demonstrate the superior performance of IoT-SCNet, achieving remarkable identification accuracies of 99.83% on UNSW, 97.50% on Yourthings, and 99.34% on CIC IoT datasets.

Placement is a critical stage for VLSI routability optimization. A placement engine without considering the layout congestion might lead to poor solutions with routing failures. This paper introduces a Coulomb force-based global placement framework that addresses global and local routing congestions. We first present a routing path-based cell padding strategy for local congestion mitigation. Then, we construct a routability-aware placement model that utilizes virtual Coulomb forces to eliminate crucial global congestion. Compared with a leading academic placer, RePlAce, and the advanced commercial tool, Innovus, the experimental results on industrial benchmark suites show that our proposed algorithm achieves the best routability within the shortest runtime.

Placement is a critical stage for VLSI timing closure. A global placer without considering timing delay might lead to inferior solutions with timing violations. This paper proposes an electrostatics-based timing optimization method for VLSI global placement. Simulating the optimal buffering behavior, we first present an analytical delay model to calculate each connection delay accurately. Then, a timing-driven block distribution scheme is developed to optimize the critical path delay while considering the path-sharing effect. Finally, we develop a timing-aware precondition technique to speed up placement convergence without degrading timing quality. Experimental results on industrial benchmark suites show that our timing-driven placement algorithm outperforms a leading commercial tool by 6.7% worst negative slack (WNS) and 21.6% total negative slack (TNS).

Static IR drop analysis is a fundamental and critical task in chip design since the IR drop will significantly affect the design's functionality, performance, and reliability. However, the process of IR drop analysis can be time-consuming, potentially taking several hours. Therefore, a fast and accurate IR drop prediction is paramount for reducing the overall time invested in chip design. In this paper, we propose a global and local attention-based Inception U-Net for static IR drop prediction. Our U-Net incorporates the Transformer, CBAM, and Inception architectures to enhance its feature capture capability at different scales and improve the accuracy of predicted IR drop. Moreover, we propose 4 new features, which enhance our model with richer information. Finally, to balance the sampling probabilities across different regions in one design, we propose a series of novel data spatial adjustment techniques, with each batch randomly selecting one of them during training. Experimental results demonstrate that our proposed algorithm can achieve the best results among the winning teams of the ICCAD 2023 contest and the state-of-the-art algorithms.

Routability estimation identifies potentially congested areas in advance to achieve high-quality routing solutions. To improve the routing quality, this paper presents a deep learning-based congestion estimation algorithm that applies the estimation to a global router. Unlike existing methods based on traditional compressed 2D features for model training and prediction, our algorithm extracts appropriate 3D features from the placed netlists. Furthermore, an improved RUDY (Rectangular Uniform wire DensitY) method is developed to estimate 3D routing demands. Besides, we develop a congestion estimator by employing a U-net model to generate a congestion heatmap, which is predicted before global routing and serves to guide the initial pattern routing of a global router to reduce unexpected overflows. Experimental results show that the Pearson Correlation Coefficient (PCC) between actual and our predicted congestion is high at about 0.848 on average, significantly higher than the counterpart by 21.14%. The results also show that our guided routing can reduce the respective routing overflows, wirelength, and via count by averagely 6.05%, 0.02%, and 1.18%, with only 24% runtime overheads, compared with the state-of-the-art CUGR global router that can balance routing quality and efficiency very well. In particular, our work provides a new generic machine learning model for not only routing congestion estimation demonstrated in this paper, but also general layout optimization problems.