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Kedong Fang

dblp:273/7062 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0002-2387-4160ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Databases, data mining, and information retrieval
1 paper
Indexing and storage engines · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Indexing and storage engines
b+-tree
0.412020
?Tree: a Persistent B+-Tree with Low Tail Latency · Proc. VLDB Endow. 2020
Indexing and storage engines › b+-tree
persistent b+-tree
0.412020
?Tree: a Persistent B+-Tree with Low Tail Latency · Proc. VLDB Endow. 2020
Memory systems
non-volatile memory
0.112020
?Tree: a Persistent B+-Tree with Low Tail Latency · Proc. VLDB Endow. 2020
YearPublicationVenuePosition
2023 TH-iSSD: Design and Implementation of a Generic and Reconfigurable Near-Data Processing Framework
abstract
We present the design and implementation of TH-iSSD, a near-data processing framework to address the data movement problem. TH-iSSD does not pose any restriction to the hardware selection and is highly reconfigurable—its core components, such as the on-device compute unit (e.g., FPGA, embedded CPUs) and data collectors (e.g., camera, sensors), can be easily replaced to adapt to different use cases. TH-iSSD achieves this goal by incorporating highly flexible computation and data paths. In the data path, TH-iSSD adopts an efficient device-level data switch that exchanges data with both host CPUs and peripheral sensors; it also enables direct accesses between the sensing, computation, and storage hardware components, which completely eliminates the redundant data movement overhead, and thus delivers both high performance and energy efficiency. In the computation path, TH-iSSD provides an abstraction offilestreamfor developers, which abstracts a collection of data along with the related computation task as a file. Since existing applications are familiar with POSIX-like interfaces, they can be ported on top of our platform with minimal code modification. Moreover, TH-iSSD also introduces mechanisms includingpipelined near-data processingandpriority-aware I/O schedulingto make TH-iSSD perform more effectively. We deploy TH-iSSD to accelerate two types of applications: the content-based information retrieval system and the edge zero-streaming system. Our experimental results show that TH-iSSD achieves up to 1.6× higher throughput and 36% lower latency thancompute-centricdesigns.
Jiwu Shu, Kedong Fang, Youmin Chen
ACM Trans. Embed. Comput. Syst.2
2020 ?Tree: a Persistent B+-Tree with Low Tail Latency
Youmin Chen, Youyou Lu, Kedong Fang, Qing Wang 0031, Jiwu Shu
Proc. VLDB Endow.3