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Mitsuhiro Makino

dblp:274/0785 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › concurrent system
multitasking		 0.011988
Vector and parallel processing of the nuclear reactor transient analysis code RELAPS · SC 1988
Parallel and multicore computing
parallel programming models		 0.011988
Vector and parallel processing of the nuclear reactor transient analysis code RELAPS · SC 1988
Processor architecture and microarchitecture
vector processing		 0.011988
Vector and parallel processing of the nuclear reactor transient analysis code RELAPS · SC 1988

Methods — techniques the papers use, named apart from their topics

vectorization · 0.0multitasking · 0.0
YearPublicationVenuePosition
1988 Vector and parallel processing of the nuclear reactor transient analysis code RELAPS
abstract
An experiment on vector processing and multitasking of the nuclear reactor transient analysis code RELAPS has been carried out. Vector processing and multitasking were achieved by using the independency of the spatial meshes. The vectorization ratio is 83%. The performance ratio in the vector mode to that in the scalar mode is about three on the FACOM VP-100. For multitasking the spatial meshes are halved, and each group of meshes is processed on a different processor. The effect of multitasking was estimated from the CPU time on the FACOM VP-100, which is a single-processor system. The improvement of wall clock time will be about 1.6 for parallelized subroutines. The total improvement of wall clock time will be about 1.2 because of parallelization ratio 45%.>
Misako Ishiguro, Mitsuhiro Makino, Naohisa Shinozawa
 SC2