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Xipeng Li

dblp:274/1507 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 55% Parallel and multicore computing · 27% Hardware accelerators and domain-specific architectures · 18%
Databases, data mining, and information retrieval
1 paper
Information retrieval · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing › GPU computing
GPU algorithms
0.712023
Parallel Top-K Algorithms on GPU: A Comprehensive Study and New Methods · SC 2023
Parallel and multicore computing
parallel algorithms
0.712023
Parallel Top-K Algorithms on GPU: A Comprehensive Study and New Methods · SC 2023
GPUs and heterogeneous computing
top-k selection
0.712023
Parallel Top-K Algorithms on GPU: A Comprehensive Study and New Methods · SC 2023
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.412020
Accelerating sparse DNN models without hardware-support via tile-wise sparsity · SC 2020
Information retrieval › similarity search
top-k retrieval
0.212023
Parallel Top-K Algorithms on GPU: A Comprehensive Study and New Methods · SC 2023
Machine learning › Efficient and distributed learning › model compression
pruning
0.112020
Accelerating sparse DNN models without hardware-support via tile-wise sparsity · SC 2020

Methods — techniques the papers use, named apart from their topics

radix select · 1.3parallel insertion · 1.3tile-wise sparsity pattern · 0.9algorithm-software co-design · 0.9
YearPublicationVenuePosition
2023 Parallel Top-K Algorithms on GPU: A Comprehensive Study and New Methods
abstract
The top-K problem is an essential part of many important applications in scientific computing, information retrieval, etc. As data volume grows rapidly, high-performance parallel top-K algorithms become critical. We propose two parallel top-K algorithms, AIR Top-K (Adaptive and Iteration-fused Radix Top-K) and GridSelect, for GPU. AIR Top-K employs an iteration-fused design to minimize CPU-GPU communication and device data access. Its adaptive strategy eliminates unnecessary device memory traffic automatically under various data distributions. GridSelect can process data on-the-fly. It adopts a shared queue and parallel two-step insertion to decrease the frequency of costly operations. We comprehensively compare 8 open-source GPU implementations and our methods for a wide range of problem sizes and data distributions. For batch sizes 1 and 100, respectively, AIR Top-K shows 1.98--21.48× and 8.01--574.78× speedup over previous radix top-K algorithm, and 1.44--7.34× and 1.38--31.91× speedup over state-of-the-art methods. GridSelect shows up to 882.29× speedup over its baseline.
Jingrong Zhang, Akira Naruse, Xipeng Li
SC3
2020 Accelerating sparse DNN models without hardware-support via tile-wise sparsity
abstract
Network pruning can reduce the high computation cost of deep neural network (DNN) models. However, to maintain their accuracies, sparse models often carry randomly-distributed weights, leading to irregular computations. Consequently, sparse models cannot achieve meaningful speedup on commodity hardware (e.g., GPU) built for dense matrix computations. As such, prior works usually modify or design completely new sparsity-optimized architectures for exploiting sparsity. We propose an algorithm-software co-designed pruning method that achieves latency speedups on existing dense architectures. Our work builds upon the insight that the matrix multiplication generally breaks the large matrix into multiple smaller tiles for parallel execution. We propose a tiling-friendly “tile-wise” sparsity pattern, which maintains a regular pattern at the tile level for efficient execution but allows for irregular, arbitrary pruning at the global scale to maintain the high accuracy. We implement and evaluate the sparsity pattern on GPU tensor core, achieving a 1.95× speedup over the dense model.
Cong Guo 0003, Bo Yang Hsueh, Jingwen Leng, Yuxian Qiu, Yue Guan 0003, Zehuan Wang 0001, Xiaoying Jia 0001, Xipeng Li, Minyi Guo, Yuhao Zhu 0001
SC8