Preet Derasari

dblp:274/3642 · DBLP profile ↗
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4ranked-venue papers
3as first author
4since 2021 · last 2024
0000-0002-2177-393XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021
YearPublicationVenuePosition
2024 Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions
abstract
Embedded systems are evolving in complexity, leading to the emergence of multiple threats. The co-design and execution of software on the embedded systems further exacerbate the attack surface, making them more vulnerable to sophisticated attacks. As embedded systems are used in critical areas, ensuring their security is crucial. In this special session paper, primarily four major topics regarding embedded systems’ security are discussed. Firstly, this paper initially explores timing channel analysis at a microarchitectural level in heterogeneous hardware to address the security challenges. It then delves into exploring software-based fuzzing techniques to detect vulnerabilities and enhance embedded system security. Additionally, the paper discusses strategies for improving security in IoT devices with a layered defense strategy known as Snowflake IoT. Finally, it examines approaches to securing large and complex monolithic systems. The challenges and opportunities for securing the embedded systems according to the scale and type of attacks.
Venkat Nitin Patnala, Sai Manoj Pudukotai Dinakarrao, Guru Venkataramani, Jie Chen 0020, Preet Derasari, Milos Doroslovacki, Fan Yao 0001, Hongyu Fang, Meron Zerihun Demissie, Todd M. Austin, Lauren Biernacki, Saket Upadhyay, Arnabjyoti Kalita, Ashish Venkat
CASES5
2024 EPIC: Efficient and Proactive Instruction-level Cyberdefense
abstract
In the evolving cyber-threats landscape, conventional security defenses often fall short, relying on reactive countermeasures that limit their ability to address the attack vectors that adapt over time. Proactive defense strategies, such as cyber deception and Moving Target Defense (MTD), aim to pre-emptively control the attack surface and redirect or drain the adversaries actively. Currently, their adoption is hindered by high runtime costs that further limit their scalability for real-world deployments.
Preet Derasari, Guru Venkataramani
ACM Great Lakes Symposium on VLSI1
2023 Mayalok: A Cyber-Deception Hardware Using Runtime Instruction Infusion
abstract
Rapid rise in malware attacks has added significant costs to cyber operations. As adversaries evolve, there is a growing need for fast, targeted defenses that effectively guard computer systems against these cyber-attacks. Cyber-deception is an increasingly adopted defense strategy with its ability to continually engage with adversaries and deploy counter-measures proactively by manipulating the malware program execution flow to non-useful states for the attacker. This paper introduces Mayalok, a novel hardware-based cyber-deception framework to combat malware through runtime instruction infusion. Mayalok employs hardware deception primitives to transparently insert or skip malware program instructions during runtime and deliver the attackers a deceptive view of the system state. We evaluate and demonstrate the deception efficacy of the Mayalok framework on malware samples representing various attack vectors: Ransomware, InfoStealers, Buffer overflow, and Side-channels.
Preet Derasari, Kailash Gogineni, Guru Venkataramani
ASAP1
2023 MAYAVI: A Cyber-Deception Hardware for Memory Load-Stores
abstract
Rapid evolution of security attacks presents a perpetual challenge to computer system defenders in terms of continuously upgrading their defense capabilities and being aware of adversarial tactics. Emerging technologies like cyber-deception offer the unique advantage of intelligently surveying hostile behavior while actively safeguarding sensitive assets by manipulating the malware execution flow to non-useful states or misrepresenting critical data.
Preet Derasari, Kailash Gogineni, Guru Venkataramani
ACM Great Lakes Symposium on VLSI1