This paper proposes a novel redundancy-based approach to drastically relax the matching requirements of CDACs and employing a cost-effective digital calibration method to improve linearity. The proposed architecture features a 3-segment CDAC with two redundant bits, which effectively reduces the overall DAC area and improves the DAC’s linearity. A 15-bit version of the DAC has been implemented in TSMC 0.18 μm technology, occupying a total area of 0.010 mm2. The design is validated through simulations in Cadence Spectre and calibration in MATLAB, resulting in worst-case integral nonlinearity (INL) and differential nonlinearity (DNL) of less than 0.5 LSB and 1 LSB, respectively, across 200 Monte-Carlo iterations.

Level shifters form an indispensable part of modern system on chips (SoCs) with their use encompassing multi-VDD logic designs [1], voltage stacking designs[2] and high voltage designs[3]. Traditionally, level shifters have been characterized using energy-delay curves (or correspondingly the energy-delay product) [2]. All the aforementioned applications provide the level shifter’s higher supply voltage through an external pin. Also, the primary objective in the previously mentioned applications has been reduction in energy consumption. Thus, energy-delay product is an appropriate figure-of merit (FOM) for these applications. However, unlike these applications certain analog/mixed signal(AMS) applications like that in [4] employ charge-pumps to generate the higher supply voltages. The FOM of energy-delay product is no longer appropriate in these cases for two reasons. First, the use of energy delay curves to characterize and choose the appropriate level shifter architecture ignores the energy consumed by the charge pumps to generate the higher voltages and can eventually lead to an overall larger energy consumption. Secondly, since the current from the higher voltage is provided through a charge reservoir (capacitor in most cases), voltage droop during switching should also be accounted by the FOM. Optimizing the energy-delay product does not account for this effect. We therefore argue that charge-delay product (or correspondingly the charge-delay curves) is a better FOM to compare level shifters to be used in such applications. The “charge” of concern here refers to the charge consumed through the higher supply voltage. One might argue that charge-delay optimization is equivalent to energy-delay optimization. However, we would like to emphasize the fact that our objective is to obtain the optimization between the charge consumed from the higher supply voltage and the delay of the level shifter. This FOM allows for trading off higher energy consumption from the lower supply voltage for a lower charge consumption from the higher supply voltage.

On-chip testing for analog/mixed signal circuits helps improve reliability of safety-critical systems by enabling infield testing. It also alleviates the problems of increasing test costs. A low-cost high accuracy stimulus generator for on-chip spectral testing is proposed. The generator uses a low-cost DAC which requires minimal design and re-engineering efforts, in conjunction with INL based digital pre-distortion to calibrate its linearity performance. DAC output measurement, DAC INL estimation and DAC linearity calibration are all performed on-chip. Measurement results in 40nm bulk CMOS technology demonstrate that the circuit is capable of producing a rail-to-rail differential signal with THD of -75 dB and SFDR of 79dB. The proposed solution is a major step forward in demonstrating the feasibility of synthesizable built-in-test solutions for high-accuracy embedded analog and mixed signal functions.