This work presents a supervised machine learning (ML) technique to suppress static and dynamic errors in time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converters (ADCs). Traditional methods rely on high-speed buffers and complex calibration algorithms to address reference ripple, gain mismatch, timing mismatch, and offset mismatch, increasing area/cost and design complexity. By contrast, the proposed ML-based approach uses a low-speed SAR ADC to digitally correct these errors, enhancing performance and lowering power consumption without requiring implicit knowledge of error sources or complex calibration procedures. The proposed ML calibration is demonstrated on a 2-channel time-interleaved ADC test-chip fabricated in 28nm CMOS and improves SNDR/SFDR by more than 21/38dB respectively.

This work presents a machine learning (ML) technique to suppress reference ripple errors in successive approximation register (SAR) analog-to-digital converter (ADC). Reference voltage ripple due to switching in SAR ADC introduces dynamic error which manifests as spurs in the output spectrum and limits ADC resolution. Conventional techniques to suppress reference ripple require large decoupling capacitor and high-speed reference voltage buffer which consume large area and power. The proposed ML approach uses a supervised technique in which a low-speed 10MHz SAR ADC is used for learning and correcting reference ripple error in a 200MHz SAR ADC. Simulated in 28nm CMOS technology, the proposed ML approach reduces overall ADC power consumption by 4.9x without degrading performance.

Over the years, successive approximation register (SAR) analog-to-digital converter (ADC) designs have adopted different techniques to correct static and dynamic errors. This work proposes a machine-learning (ML) approach that uses a single model to correct both static and dynamic errors without requiring prior knowledge of these errors or complex design efforts. The proposed technique derives a custom feature set from the ADC output and uses supervised learning technique with a low-speed reference ADC to learn a representation of the ADC errors and correct them continuously in the back-end. The proposed ML correction is demonstrated on a 10-bit SAR ADC fabricated in 65nm CMOS and improves SNDR and SFDR by more than 8dB and 25dB respectively. The proposed ML technique adopts online learning and adaptively updates all the model weights individually to achieve fast convergence.

This work presents a supervised machine learning (ML) technique to simultaneously suppress static and dynamic errors in successive approximation register (SAR) analog-to-digital converter (ADC) and a delta-sigma digital-to-analog converter (DAC). Capacitor mismatches, reference ripple and kick-back errors in switched-capacitor circuits, and element mismatch and inter-symbol interference (ISI) errors are the sources of static and dynamic errors in SAR ADC and $\Delta \Sigma$ DAC respectively. Conventional approaches employ dynamic element matching, error-shaping and high-speed reference buffers for suppressing these errors at the cost of increased power/area penalties and complex design efforts. The proposed ML approach uses a supervised technique in which a low-speed SAR ADC is used for learning and correcting dynamic errors digitally in both ADC and DAC using a single on-chip ML circuit. The key advantages of the proposed approach are - detailed knowledge of error generation mechanisms are not needed for calibration, reduction in power consumption and improvement in data converter performance.

This work presents a fusion artificial intelligence (AI) framework that combines patient electronic medical record (EMR) and physiological sensor data to accurately predict early risk of sepsis 4 hours before onset. The fusion AI model has two components - an on-chip AI model that continuously analyzes patient electrocardiogram (ECG) data and a cloud AI model that combines EMR and prediction scores from on-chip AI model to predict fusion sepsis onset score. The on-chip AI model is designed using analog circuits for high energy efficiency that allows integration with resource constrained wearable device. The on-chip AI reduces by 4.5× compared to digital baseline, and by 4× compared to state-of-the-art bio-medical AI ICs. Combination of EMR and sensor physiological data improves prediction performance compared to EMR or physiological data alone, and the late fusion model has an accuracy of 92.2% in predicting sepsis 4 hours before onset. The key differentiation of this work over existing sepsis prediction literature is the use of single modality patient vital (ECG) and simple demographic information, instead of comprehensive laboratory test results and multiple vital signs.