Deterministic Network Calculus (DNC) provides a rigorous algebra for worst-case performance analysis of networks. It allows researchers to compute bounds on worst-case characteristics of systems through algebraic expressions that may appear simple on paper but often require heavy computations, making software support essential. Libraries such as Nancy offer a rich API for DNC computations in C#, but they require programming expertise. In contrast, RTaW’s min-plus playground (MPPG) provides a simpler, calculator-like syntax for DNC computations; however, it is proprietary and web-hosted, limiting offline use and reproducibility. We present nancy-playground, an open-source, locally runnable console that implements the same MPPG syntax while executing computations through the Nancy library. This tool enables reproducible scripting, interactive exploration, and a seamless transition to full programs by converting MPPG scripts into C# code. In this paper, we describe the design and implementation of nancy-playground, as well as its main features for researchers and practitioners in the DNC community.

Networks with hop-by-hop flow control occur in several contexts, from data centers to systems architectures (e.g., wormhole-routing networks on chip). A worst-case end-to-end delay in such networks can be computed using Network Calculus (NC), an algebraic theory where traffic and service guarantees are represented as curves in a Cartesian plane. NC uses transformation operations, e.g., the min-plus convolution, to model how the traffic profile changes with the traversal of network nodes. NC allows one to model flow-controlled systems, hence one can compute the end-to-endservice curvedescribing the minimum service guaranteed to a flow traversing a tandem of flow-controlled nodes. However, while the algebraic expression of such an end-to-end service curve is quite compact, its computation is often intractable from an algorithmic standpoint: data structures tend to grow quickly to unfeasibly large sizes, making operations intractable, even with as few as three hops. In this paper, we propose computational and algebraic techniques to mitigate the above problem. We show that existing techniques (such as reduction tocompact domains) cannot be used in this case, and propose an arsenal of solutions, which include methods to mitigate the data representation space explosion as well as computationally efficient algorithms for the min-plus convolution operation. We show that our solutions allow a significant speedup, enable analysis of previously unfeasible case studies, and - since they do not rely on any approximation - still provide exact results.

Due to the trends of centralizing the EIE architecture and new computing-intensive applications, high-performance hardware platforms are currently finding their way into automotive systems. However, the Systems-on-Chip (SoCs) currently available on the market have significant weaknesses when it comes to providing predictable performance for time-critical applications. The main reason for this is that these platforms are optimized for average-case performance. This shortcoming represents one major risk in the development of current and future automotive systems. In this paper we describe how highperformance and predictability could (and should) be reconciled in future HW /SW platforms. We believe that this goal can only be reached via a close collaboration among system suppliers, IP providers, semiconductor companies, and OS/hypervisor vendors. Furthermore, academic input will be needed to solve remaining challenges and to further improve initial solutions.

Computing Systems are evolving towards more complex, hetero-geneous systems where multiple computing cores and accelera-tors on the same system concur to improve computing resources utilization, resources re-use and the efficiency of data sharing across workloads. Such complex systems require equally complex tools and models to design and engineer them so that their use-case requirements can be satisfied. Adaptive Traffic Profiles (ATP) introduce a fast prototyping technology, which allows one to model the dynamic memory behavior of computer system de-vices when executing their workloads. ATP defines a standard file format and comes with an open source transaction generator engine written in C++. Both ATP files and the engine are porta-ble and pluggable to different host platforms, to allow workloads to be assessed with various models at different levels of abstraction. We present here the ATP technology developed at Arm and published in [5]. We present a case-study involving the usage of ATP, namely the analysis of the worst-case latency at a DRAM controller, which is assessed via two separate toolchains, both using traffic modelling encoded in ATP.