Xiang-Min Yang

dblp:275/4936 · DBLP profile ↗
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4ranked-venue papers
1as first author
3since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 3 since 2021
YearPublicationVenuePosition
2024 LOOPLock 3.0: A Robust Cyclic Logic Locking Approach
abstract
Cyclic logic locking is a cutting-edge hardware security method developed to defend against SAT Attack. It introduces cycles into the original circuit, which can cause the circuit to either get trapped in an endless loop or generate incorrect outputs if an incorrect key is used. Recently, a new cyclic logic locking method called LOOPLock 2.0 was proposed. Its primary feature is that the circuit retains its cyclic structure regardless of whether the correct key vector is applied or not. However, LOOPLock 2.0 can still be successfully attacked using locking structure analysis in the state-of-the-art. As a result, this paper presents a more robust cyclic logic locking approach LOOPLock 3.0 to counteract state-of-the-art attacks. The experimental results validate the effectiveness of the proposed approach.
Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang
ASPDAC2
2022 An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0
abstract
Cyclic logic locking is a new type of SAT-resistant techniques in hardware security. Recently, LOOPLock 2.0 was proposed, which is a cyclic logic locking method creating cycles deliberately in the locked circuit to resist SAT Attack, CycSAT, BeSAT, and Removal Attack simultaneously. The key idea of LOOPLock 2.0 is that the resultant circuit is still cyclic no matter the key vector is correct or not. This property refuses attackers and demonstrates its success on defending against attackers. In this paper, we propose an unlocking approach to LOOPLock 2.0 based on structure analysis and SAT solvers. Specifically, we identify and remove non-combinational cycles in the locked circuit before running SAT solvers. The experimental results show that the proposed unlocking approach is promising.
Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
ICCAD2
2022 LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach
abstract
LOOPLock is the state-of-the-art cyclic logic locking method in hardware security. LOOPLock is able to invalidate SAT Attack, Removal Attack, and CycSAT simultaneously by introducing two types of cycle pairs in a circuit. In this work, we analyze LOOPLock’s locking mechanism and propose an attacking approach based on locking structure analysis. Furthermore, to defend the new attack, we propose LOOPLock 2.0, which strengthens the original cyclic logic locking method—LOOPLock. Experimental results show the efficiency and effectiveness of the proposed attacking approach to LOOPLock and the high defense capability of LOOPLock 2.0.
Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2020 LOOPLock: Logic Optimization-Based Cyclic Logic Locking
abstract
SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method.
Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, Chun-Yao Wang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4