Tri-level current-steering digital-to-analog converters (DACs) offer an appealing balance between resolution and static linearity, making them attractive to be employed as feedback DAC in high-resolution continuous-time Delta-Sigma-Modulator (CTDSM). However, they are susceptible to non-linearity caused by dynamic, signal-dependent switching errors degrading the overall performance. While such errors have been thoroughly analyzed in literature for single-bit current-steering DACs, they have not been thoroughly investigated for tri-level current-steering DACs. As a result, this paper investigates the sources of these errors and demonstrates their severity by analysis and simulations employing a tri-level DAC in an exemplary CTDSM. In addition, techniques for mitigating dynamic errors, including device sizing and switching schemes, are discussed to help mitigate the non-linearity.

As AI and its applications evolve, efficient hardware is required to run the novel algorithms. Compute platforms with a high degree of parallelism, such as matrix-vector multipliers, meet the need to process large homogeneous loads of operations. However, most of the matrix-vector multiplications required by the AI algorithms are larger than what the actual hardware supports. The operations must therefore be tiled into blocks that fit on the given hardware. Finally, the partial sums generated by the hardware for each tile must be accumulated or concatenated into the complete result. Especially with mixed-signal compute-in-memory architectures, this can lead to quantization on two levels. First, an ADC quantizes the partial sums generated for each tile. Then, the algorithm performs another quantization of the final result to limit bitwidth and resource consumption in adjacent computations. While quantizing only the partial sums or only the final results has been studied extensively, the combination of the two has yet to be investigated. This work introduces a simulator to understand the effects of quantization caused by multiple quantization steps on different levels. It is based on a generic, stochastic representation of value probabilities using histograms. Common operations such as scaling, rounding, and accumulation are implemented in this representation, allowing the effect of quantization to be studied in a matrix-vector-multiplier application. It is shown, that the selection of tilesize, ADC bitwidth and clipping technique form a complex trade-off, which can be solved using PSumSim. PSumSim is available under https://github.com/Joschua-Conrad/PSumSim.

Dedicated neural-network inference-processors improve latency and power of the computing devices. They use custom memory hierarchies that take into account the flow of operators present in neural networks and convolutional layers. For efficient implementation, such network topologies can greatly benefit from hardware-cost optimization using automated network-architecture search. Thereby, cost functions predict the suitability of a network topology for a given type of inference hardware. A differentiable neural-architecture search that optimizes both weights and topology in a single training requires cost models to be differentiable in the dimensions of weight and activation matrices. State-of-the-art differentiable cost models require time-consuming system-level measurements or simulation results, or do not encounter the hardware structure at all. This work presents a simple yet effective procedure for deriving a differentiable neural-network-accelerator cost-model that is suitable for any type of accelerator. It is based on hardware-independent parameterization and a novel differentiable divide-ceil function, as well as hardware-specific modeling. The resulting differentiable model can be reconfigured to the actual hardware size and memory structure to predict the inference energy for an exact network topology. The modeling and prediction are demonstrated for a state-of-the-art SRAM-based inference-accelerator and for the Eyeriss accelerator, inferring different state-of-the-art neural networks, resulting in excellent agreement with measured hardware.

This paper introduces an Artificial Neural Network (ANN) to predict the stability of Delta-Sigma modulators (DSMs) and, furthermore, shows its beneficial employment in a genetic optimization algorithm. Since a DSM is a non-linear system, its stability often can’t be predicted by simple algebra. Therefore, a new approach predicting the stability of DSMs using an ANN is presented in this work. It is shown how the data generation and training of such a network can be done. Furthermore, the derivation of high-level coefficients for DSMs is a tedious task, which is often solved by time consuming simulations. The application of the derived ANN in a genetic algorithm to find these high-level coefficients leads to the significant time savings of close to 50%.