In order for raw sensory data to be processed by spiking neural networks (SNNs) an intermediary spike encoder must translate that data into a spike-train. Since there is no one-size-fits-all encoding method suitable for every neuromorphic application, the necessary encoding scheme differs from one implementation to the next. A similar circumstance exists concerning the encoding interval, or frame, that a spike-train is produced for. Although research exists on individual encoding schemes with a rationale for excluding other methods for a particular application, no neuromorphic implementation has addressed a dedicated hardware encoder that is compatible with multiple encoding methods. In this study, we introduce an encoder module which supports three major encoding schemes. The encoding method, as well as the encoding frame duration, can be easily tweaked at runtime. Both FPGA and VLSI implementations have been created for this encoder that are highly scalable and fast, with the latter running with a clock frequency of up to 530 MHz in a 65-nm process. The small area and power footprint of this design makes it attractive for any hardware-based neuroprocessor without needing any external software, or hardware, based process for data encoding.

Neuromorphic computing systems have emerged as powerful computation tools in the field of object recognition and control systems. However, training these systems, which are usually characterized by recurrent connectivity, requires abundant computational resources: memory, computation, data, and time. Reservoir computing (RC) framework reduces this high computational training cost by focusing the training effort on only a small subset of connections thus allowing these systems to be amenable to hardware implementation. Using memristors to construct these reservoir computers reduce the area/power consumption even further. However, the inherent variability of memristors poses specific challenges. Here, we conduct an in-depth reliability analysis of challenges posed by HfO2 memristors, including cycle-to-cycle variability, read/write noise, and conductance drift in the context of RC hardware. We also explore plasticity mechanisms such as Spike-Timing Dependent Plasticity (STDP) within the scope of the spiking recurrent neural networks (SRNN) reservoir and their impact on memristor conductance drift (MCD). We present a chaotic time series prediction task applied to a Python model of the constrained hardware design achieving very low Normalized Root Mean Square Error (NRMSE) of 2 × 10-3. The analog neuron and memristive synapse circuits employed for constructing the SRNN are simulated in Cadence Spectre and the energy consumption for the Mackey-Glass (MG) time-series prediction task was found to be approximately 90 nJ.

Neuromorphic computing is a leading option for non von-Neumann computing architectures. With it, neural networks are developed that derive architectural inspiration from how the brain operates with neurons, synapses, and spikes. These networks are often implemented in either software or hardware based neuroprocessors designed to handle specific tasks efficiently. Even if implemented in hardware, software emulation is instrumental in determining the worthwhile features and capabilities of the architecture. In this work two novel neuroprocessors are introduced: the software-based RISP neuroprocessor, and the RAVENS hardware neuroprocessor. Several benchmark tests using control applications are performed with each neuroprocessor configured in various ways to evaluate their comparative performance and training properties.

In this work we describe the design, implementation, and testing of the first neuromorphic robot capable of obstacle avoidance, grid coverage, and targeting controlled by the second generation Dynamic Adaptive Neural Network Array (DANNA2) digital spiking neuromorphic processor. The simplicity of the DANNA2 processor along with the TENNLab hardware/software co-design framework allows for compact spiking networks that can run efficiently on a small, resource-constrained, platform such as a Xilinx Artix-7 field-programmable gate array. Additionally, we present the dynamic reconfigurability of DANNA2 arrays as a method of realizing complex, multi-objective tasks on hardware that is restricted to relatively small networks.

Neuromorphic computing is one promising post-Moore's law era technology, which takes inspiration from biological brains to perform computing tasks. The human brain contains billions of neurons with trillions of synapses and as neuromorphic hardware systems scale to larger and larger sizes, the communication system used to transfer information between neuromorphic elements and traditional computers must scale to keep up. In prior work, we describe the use of a separate neuromorphic array communications controller to support low-latency, high-throughput communication between our neuromorphic systems and a traditional computer. In this work, the neuromorphic array communications controller is used to support the scaling of a neuromorphic development system which uses multiple neuromorphic processors arranged in a two-dimensional array. The neuromorphic array communications controller, along with scalable local connections, is used to create a scalable neuromorphic platform to enable the development and testing of large neuromorphic network arrays.