This paper proposes a four-level pulse amplitude modulation (PAM-4) half-rate receiver, incorporating a current-reuse analog front-end (AFE) and a single-loop half-rate reference-less bang-bang clock and data recovery (BBCDR) in a 40-nm CMOS process. The inverter-based AFE is introduced to compensate for the channel insertion loss efficiently, utilizing a continuous-time linear equalizer (CTLE) that works in conjunction with feed-forward mid-frequency equalization and a variable gain amplifier (VGA) that employs a complementary-Gilbert gm-cell for enhanced current efficiency. The gm-transimpedance-amplifier (Gm-TIA) topology is employed in the AFE to extend the gain-bandwidth (GBW) product. To overcome the design challenges of high-speed clock generation and distribution, the BBCDR adopts a half-rate architecture. Two asymmetric locking points (LPs) are adopted for the bang-bang phase detector (BBPD) by the clock-phase-selection (CPS) scheme and the hybrid control circuit (HCC) is adopted to automate the frequency acquisition. To eliminate the impact of the middle transition of the PAM-4 signal and enhance the jitter performance of the proposed PAM-4 receiver, the pattern-selection technique is adopted in the proposed pattern-based BBPD (PB-BBPD). The measurement results demonstrate that the receiver can compensate for −8.5 dB channel loss at 12.5 GHz and automatically eliminate the frequency errors with the single-loop architecture. Moreover, by incorporating the proposed PB-BBPD, the PAM-4 receiver achieves an improved jitter performance with a power efficiency of 2.47 pJ/bit.

This paper presents a$2\times 80$Gb/s single-ended trans-admittance trans-impedance (TAS-TIS) 4-level pulse amplitude modulation (PAM-4) receiver with crosstalk cancellation and signal reutilization technique in 28-nm CMOS. Based on the TAS-TIS architecture, to achieve a precise cancellation of the far-end crosstalk, a common mode gain rejection methodology is proposed in the balanced differentiator, ensuring low gain mismatch and low phase skew. Moreover, the proposed Gm-doubler technique in the TAS-TIS architecture enhances the gain of the adder under limited supply voltage conditions. By employing the series peaking combined with an active inductor in the adder, the bandwidth of adder is improved by a factor of 2.2, and the group delay variation is effectively optimized by 65%. The proposed current-mirror-based continuous-time linear equalizer (CTLE) provides high-frequency and low-frequency compensation with 25% power saving. Overall, the measurement results of the proposed receiver demonstrate$2\times 80$Gb/s PAM-4 eyes with an efficiency of 0.83 pJ/bit/lane and$2\times 56$Gb/s non-return-to zero (NRZ) eyes over a pair of PCB traces with 13 dB loss at 20 GHz and 28 dB loss at 28 GHz, respectively.

A 112-Gb/s single-ended (SE) four-level pulse amplitude modulation (PAM-4) transceiver front-end for the reach-extension module in long-reach (LR) link is proposed. The receiver front-end features an SE-to-differential (S2D) amplifier and a continuous-time linear equalizer (CTLE). Asymmetric inductive peaking, compensation capacitance, and current blending techniques are employed in S2D to eliminate the mismatch at the pseudo-differential outputs. A compact and peaking-enhanced CTLE is achieved by the inductor reused technique. The transmitter front-end is based on a differential-to-SE (D2S) driver where the negative capacitance technique is proposed to extend its bandwidth. Fabricated in 130-nm SiGe BiCMOS technology, our SE transceiver front-end demonstrates a data rate of 112-Gb/s PAM-4 at a 20-dB channel loss with an FoM of 0.09 pJ/bit/dB and BER of$3.21e$-4.

This paper presents a fully-integrated flipped-voltage-follower-based low-dropout regulator (LDO), with proposed high-gain two-stage cross-coupled error amplifier (XCEA). Besides, the effectiveness of bypass capacitors and diversified load capacitors is discussed. Consuming$\mathbf{170}-\boldsymbol{\mu} \mathbf{A}$quiescent current and occupying area of 0.019 mm2, the LDO features 25-MHz unity-gain bandwidth (UGB) at 20-mA load to satisfy fast response requirement in high-speed transmitter. The simulated voltage undershoot is 38.85 mV for a load transient current stepping from$\mathbf{1}\ \boldsymbol{\mu} \mathbf{A}$to 25 mA in 50 ps with$\boldsymbol{C}_{\mathbf{L}} =\mathbf{100}\ \mathbf{pF}$. Owing to the proposed XCEA and the filter capacitor, the PSR is measured to be -41 dB at 100 kHz and -36 dB at 1 MHz.

This article presents a low-power 1/4-rate four-level pulse amplitude modulation (PAM4) receiver with an adaptive variable-gain rectifier (AVGR)-based decoder in 28-nm CMOS technology. The PAM4 input signal is preconditioned by a continuous-time linear equalizer (CTLE) then sampled into four branches of decoders by 1/4-rate clocks. The proposed AVGR-based PAM4-to-nonreturn-to-zero (NRZ) decoder performs gain adaptation and amplitude rectification simultaneously for decoding the least significant bit (LSB). The linear sense amplifier in the AVGR is modified from a latch to achieve a high gain and low power. Compared with the full-rate receiver adopting a decoder consisting of three comparators, this design achieves a better power efficiency by employing a 1/4-rate topology and merging a variable-gain function into the decoder. Experimental results demonstrate that the receiver chip can receive and decode a 24-Gb/s 190-mVppPAM4 signal at a BER of 10-11and a bit efficiency of 1.38 pJ/bit.