In order to take full advantage of chiplet-based system synthesis methodology for HPC and AI applications in high-bandwidth memory, die-to-die designs interconnect need an overhaul breakthrough. The major reason lies in the strengthening technologies: offset-via and teardrop. They need special care in order to enhance reliability and manufacturability. Moreover, conventional signal integrity problems are required to pay attention as well. In this work, by empirical offset-via and layer assignment, we first make sure the optimized routing resources on all the redistribution layers. Then we devise an S-route detailed routing to prevent the detour and to reduce the rip-up and re-route iterations. Results show that we achieved total wire length reduction by 7% on average and total usage of RDLs by nearly 50%, compared with combined SOTA approaches.

In this paper, we depict modern system design methodologies via 3D integration along with the advance of packaging, considering system prototyping, interconnecting, and physical implementation. The corresponding challenges are presented as well.

In this article, we present a don’t-care-based threshold logic gate (TLG) minimization method for threshold logic network (TLN) optimization. We first introduce a sufficient condition for the don’t cares of a TLG to exist in a TLN and propose a logic-implication-based method to identify the don’t cares. Then, we present two different methods for minimizing the TLG with the don’t cares. The first one is an integer linear programming (ILP)-based method. We model the minimization problem as an ILP problem and propose an approach to compute the necessary constraints of the ILP formulation. The second one is a heuristic method adapted from a threshold function identification approach. In the experiments, we applied the proposed methods to two sets of TLNs generated by the up-to-date synthesis technique. The results show that, for the two sets of TLNs, the ILP-based method achieves an average of 12% and 23% area reduction without any overhead on the TLG count and logic depth. Furthermore, the heuristic method is more efficient than the ILP-based method with only a little quality loss.

This paper introduces a method to enhance an integer linear programming (ILP)-based method for transforming a 1st-order threshold logic gate (1-TLG) to a 2nd-order TLG (2-TLG) with lower area cost. We observe that for a 2-TLG, most of the 2nd-order weights (2-weights) are zero. That is, in the ILP formulation, most of the variables for the 2-weights could be set to zero. Thus, we first propose three sufficient conditions for transforming a 1-TLG to a 2-TLG by extracting 2-weights. These extracted weights are seen to be more likely non-zero. Then, we simplify the ILP formulation by eliminating the non-extracted 2-weights to speed up the ILP solving. The experimental results show that, to transform a set of 1-TLGs to 2-TLGs, the enhanced method saves an average of 24% CPU time with only an average of 1.87% quality loss in terms of the area cost reduction rate.

Threshold logic re-attracts researchers' attention recently due to the advancement of hardware realization techniques and its applications to deep learning. In the past decade, several design automation techniques for threshold logic have been proposed, such as logic synthesis and logic optimization. Although they are effective, threshold logic network (TLN) optimization based on don't cares has not been well studied. In this paper, we propose a don't-care-based node minimization scheme for TLNs. We first present a sufficient condition for don't cares to exist and a logic-implication-based method to identify the don't cares of a threshold logic gate (TLG). Then, we transform the problem of TLG minimization with don't cares to an integer linear programming problem, and present a method to compute the necessary constraints for the ILP formulation. We apply the proposed optimization scheme to two set of TLNs generated by the state-of-the-art synthesis technique. The experimental results show that, for the two sets, it achieves an average of 11% and 19% of area reduction in terms of the sum of the weights and threshold values without overhead on the TLG count and logic depth. Additionally, it completes the optimization of most TLNs within one minute.