Row-merged polar codes are a family of pre-transformed polar codes (PTPCs) with little precoding overhead. Providing an improved distance spectrum over plain polar codes, they are capable to perform close to the finite-length capacity bounds. However, there is still a lack of efficient design procedures for row-merged polar codes. Using novel weight enumeration algorithms with low computational complexity, we propose a design methodology for row-merged polar codes that directly considers their minimum distance properties. The codes significantly outperform state-of-the-art cyclic redundancy check (CRC)-aided polar codes under successive cancellation list (SCL) decoding in error-correction performance. Furthermore, we present fast simplified successive cancellation list (Fast-SSCL) decoding of PTPCs, based on which we derive a high-throughput, unrolled architecture template for fully pipelined decoders. Implementation results of SCL decoders for row-merged polar codes in a 12nm technology additionally demonstrate the superiority of these codes with respect to the implementation costs, compared to state-of-the-art reference decoder implementations.

Error correction coding (i.e., channel coding) is a key ingredient of any digital communications system. In mobile wireless communications, channel codes have evolved from simple convolutional codes in Global System for Mobile Communications (GSM) (2G), parallel concatenated (turbo) codes in Universal Mobile Telecommunications Service (UMTS) (3G), and long-term evolution (LTE) (4G), to carefully designed multirate/multilength low-density parity-check (LDPC) codes in 5G, combined with polar codes for short messages on the synchronization channel. Based on this rich history, and by accounting for the technological advances in very large-scale integration, this article will outline some recent trends in channel coding as they may be applied in 6G systems, ranging from novel approaches for short blocklengths such as automorphism ensemble decoding, via ideas of coding for multiple access, to concepts for unified coding schemes that may simplify encoding/decoding hardware at competitive error-correcting performance.

Polar codes have recently attracted significant attention due to their excellent error-correction capabilities. However, efficient decoding of Polar codes for high throughput is very challenging. Beyond 5G, data rates towards 1Tbit/s are expected. Low complexity decoding algorithms like Successive Cancellation (SC) decoding enable such high throughput but suffer on errorcorrection performance. Polar Successive Cancellation List (SCL) decoders, with and without Cyclic Redundancy Check (CRC), exhibit a much better error-correction but imply higher implementation cost. In this paper we in-depth investigate and quantify various trade-offs of these decoding algorithms with respect to error-correction capability and implementation costs in terms of area, throughput and energy efficiency in a 28nm CMOS FD-SOI technology. We present a framework that automatically generates decoder architectures for throughputs beyond 100Gbit/s. This framework includes various architectural optimizations for SCL decoders that go beyond State-of-the-Art. We demonstrate a 506Gbit/s SCL decoder with CRC that was generated by this framework.