Randomized benchmarking (RB) is widely used in the calibration process of quantum computers with the main focus on average gate fidelity. This work proposes a version with the ability of detecting user-specified faults, and successfully detected faults in simulations and real IBM quantum processors. Our proposal can evaluate error per gate (EPG) and detect faults at the same time. We have shown our FDRB successfully detect axial-tilt fault and rotation fault in both simulation and real experiments. The overhead of our proposal is the quantum native gate count increase depending on the number of faults specified by the user.

Errors caused by faults would strongly affect the correctness of noisy intermediate-scale quantum (NISQ) circuits. In this work, we propose a technique for diagnosing coherent and incoherent faults for NISQ circuits. The proposed technique contains three phases: rough diagnosis, fine diagnosis, and depolarizing diagnosis. Rough diagnosis grid searches the Bloch sphere to locate an approximate range of a coherent fault. Fine diagnosis then precisely locates the coherent fault size based on the narrowed-down search space. At last, depolarizing diagnosis measures the depolarizing fault size. We demonstrate our technique using the Qiskit simulator with noise-free and noisy backends. The diagnosis accuracy between the diagnosed faulty gates and the injected faulty gates is over 99.95%, which is better than traditional quantum process tomography under the same conditions. Our results show that the diagnosis error of coherent faults does not affect the diagnosis accuracy of depolarizing faults. Experiments on the IBM Q devices have also been performed, and results of over 99.83% diagnosis accuracy show that our technique still preserves good resolution on real quantum circuit devices.

Probabilistic error cancellation (PEC) is a promising error mitigation technique that reduces the error rate without auxiliary quantum bits. However, PEC has two problems that need to be resolved: 1) there is no good PEC technique for parameterized gates and 2) sampling overhead (SO) grows exponentially with the number of PEC mitigated gates. We first propose a parameterized gate PEC (PGPEC) that mitigates the error without fully characterizing the gates, as the original PEC requires. The result shows that the number of gates requiring characterization for a thousand random circuits can be reduced by 97% or more. We next propose two novel approaches to solving the second problem. We propose a macro gate PEC (MGPEC) technique that aggregates multiple gates as a single macro gate to reduce the exponent of the SO. MGPEC reduces the SO by 49% on the QFT7 under the IBMQ noise model, which simulates real operation conditions of quantum circuits. We propose a design diversity PEC (DDPEC) technique to reduce the exponential basis of the SO. The results show that our DDPEC with design diversity check reduces overall SO by 13% on the QFT7 circuit under the IBM Q noise model. Combining the DDPEC with the MGPEC, we can reduce overall SO by 73%.

Currently, noisy intermediate-scale quantum (NISQ) circuits may not always generate correct outputs due to noise and faults. In this work, we propose a diagnosis technique for NISQ circuits. The proposed technique contains static diagnosis and dynamic diagnosis. Static diagnosis uses a fault dictionary that contains output probability distribution for each fault. Dynamic diagnosis uses binary search to find the accurate fault locations of faulty quantum circuits. We demonstrate our technique using the Qiskit simulator with realistic noise models. We evaluate 15 benchmarks with unitary and non-unitary faults injected. Simulation results show that the average accuracy and resolution are 97.70% and 1.81. Experiments on the IBM Q devices have also been performed, and results show that our technique is feasible on real quantum circuit devices.

Testing for quantum circuits (QC) is a challenging task because QC is intrinsically probabilistic. Existing fault models for QC, such as missing gate faults, are not suitable for quantum dot QC. This paper proposes realistic fault models and fault simulation for quantum dot QC. Our fault models are based on real physical phenomenon of quantum dot devices so that they represent real defect behavior or control errors. Our fault simulation does not need to fully expand gate matrices to 2nx 2n, where n is the number of qubits. Using sparse matrix multiplication, our fault simulation saves a lot of memory and CPU time. We also calculate the test repetition of each test pattern so that we can estimate our test time. Based on fault simulation of a full adder QC, we can select a small test set of six test patterns, totally 526 repetitions, to detect all faults with 99% confidence level.

Probabilistic circuits are a potential solution for low power designs which trade off correctness for power consumption. The behavior of probabilistic circuits are more complicated than deterministic circuits because the former produce different outputs given the same inputs. We need to apply test pattern many times to obtain output distribution of probabilistic circuits. In this paper, we apply multivariate hypothesis testing to reduce pattern repetition. We also reduce overkill by tomographic testing to determine pass or fail of CUT. Experimental results show that our proposed technique can reduce pattern repetition by 82% and reduce overkill by 99%.

Researchers now use randomized benchmarking or quantum volume to test quantum circuits (QC) in the laboratory. However, these tests are long and their fault coverage is unclear. In this paper, we propose behavior fault models based on the function of quantum gates. These fault models are scalable because the number of faults is polynomial, not exponential, to the size of QC. We propose a novel test generation that uses gradient descent to generate test configuration with short length. We revise the chi-square statistical method to decide the number of test repetitions under the specified test escape and overkill. Experimental results on IBM Q systems show that our generated test configurations are effective, and our test lengths are 1,000X shorter than traditional test methods.