We propose a UNet-based foundation model and its self-supervised learning method to address two key challenges: 1)lack of qualified annotated analog layout data, and 2)excessive variety in analog layout design tasks. For self-supervised learning, we propose random patch sampling and random masking techniques automatically to obtain enough training data from a small unannotated layout dataset. The obtained data are greatly augmented, less biased, equally sized, and contain enough information for excessive varieties of qualified layout patterns. By pre-training with the obtained data, the proposed foundation model can learn implicit general knowledge on layout patterns so that it can be fine-tuned for various downstream layout tasks with small task-specific datasets. Fine-tuning provides an efficient and consolidated methodology for diverse downstream tasks, reducing the enormous human effort to develop a model per task separately. In experiments, the foundation model was pre-trained using 324,000 samples obtained from 6 silicon-proved manually designed analog circuits, then it was fine-tuned for the five example downstream tasks: generating contacts, vias, dummy fingers, N-wells, and metal routings. The fine-tuned models successfully performed these tasks for more than one thousand unseen layout inputs, generating DRC/LVS-clean layouts for 96.6% of samples. Compared with training the model from scratch for the metal routing task, fine-tuning required only 1/8 of the data to achieve the same dice score of 0.95. With the same data, fine-tuning achieved a 90% lower validation loss and a 40% higher benchmark score than training from scratch.

We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX’s performance-power trade-off was enabled by the presented generator for the first time.