The Internet-of-Things (IoT) devices feature a broad range of power, memory, and performance requirements. Ultralow-power, low-performance controllers are at one end of the spectrum, while high-performance, power-intensive systems-on-chip (SoCs) are at the other. Heterogeneous and specialized multiprocessor SoC (MPSoC) architectures have emerged as the most effective paradigm for delivering high performance and energy efficiency across a wide range of application workloads. This work introducesHeadsail, an MPSoC application-specific integrated circuit (ASIC) designed by SoC Hub at Tampere University, Finland.Headsailfeatures a 512-KiB primary data buffer, 128 KiB of shared on-chip SRAM, seven CPU cores (including four CVA6 64-bit RISC-V processors), a low power-DDR2 (LP-DDR2) memory controller, two unique chip-to-chip (C2C) interfaces, and shared peripherals.Headsailhas been successfully implemented using a TSMC 22-nm low-power CMOS technology. Testing results show that the samples can support a maximum operating frequency of 1 GHz and achieve a peak performance of 1100 giga operations per second (GOPS), with an implementation area of 25 mm2and a power-consumption range of 64 mW–1.5 W.

The TRISTAN project aims to expand and industrialize the European RISC-V ecosystem to compete effectively with existing commercial alternatives. This initiative specifically targets the critical challenges in the development of Electronic Design Automation (EDA) tools, essential for RISC-V-based solutions, by leveraging the synergy between the open-source community and industrial solutions. This paper presents an overview of the current landscape of TRISTAN's EDA flow, highlighting specific tools and methodologies that streamline the early design phases of RISC-V-based systems. We explore the unique features of these tools, emphasizing how they complement each other to strengthen the overall design process.

This paper presents a survey of functional programming languages in System-on-a-Chip (SoC) design. The motivation is improving the design productivity by better source code expressiveness, increased abstraction level in design entry, or improved automation. The survey focuses on Chisel that is one of the most potential High Level Language (HLL) based design frameworks. We include 26 papers that report implementations ranging from IP blocks to complete chips. The result is that functional programming languages are viable for SoC design and can also be deployed in production use. However, Chisel does not increase the abstraction level in a similar way as High Level Synthesis (HLS), since it is used to create circuit generators instead of direct descriptions. Additional benefit is that Chisel offloads user effort from control and connectivity structures, and makes reusability and configurability improved over traditional Hardware Description Language (HDL) designs.

Automatic code generation is used to implement Intellectual Property (IP) blocks for System-on-Chip (SoC), but the challenge is how to describe the IP as a model and what is a feasible meta-model. IEEE 1685 IP-XACT standard and many domain-specific meta-models are not compatible and tool flows are too specific for general use. We present Kamel that is a new intermediate IP meta-model. It is used to generate behavioral code to complete IP-XACT structural models. The key idea is light modeling overhead while automating the majority of the RTL IP development tasks. Kamel uses Model Driven Architecture (MDA) to integrate IP-XACT and Kamel modeling together. Python Mako template-based code generation framework is used to generated different views from the models. The compatibility with IP-XACT is demonstrated with the Kactus2 tool. Our case study is modeling and code generation for Kvazaar HEVC video intra encoder IP block on FPGA. The results confirm that the Kamel and introduced tool flow can provide 5×-10× productivity gain when measured on time spent on model entry and Lines of Code used for model entry.