From increasing rates of e-waste production to astonishing datacenter carbon emissions, the ecological effects of computing are staggering. Computer engineering and computer science students need to understand the social and environmental context of their work, and to develop practical skills required to build more sustainable solutions. Learning sustainable development skills is challenging in a traditional university classroom: meaningfully building these skills and mindsets requires holistic, student-centered approaches, including situative, experiential, and community-centered strategies. While educators and universities have begun to integrate sustainability into curricula, we propose another approach, building a community of learning through collaboration with students and the wider community. The eKitchen is a university-based community of practice, whose purpose is to give students opportunities to develop hands-on skills in electronic repair and sustainable computer engineering, reduce e-waste on campus, and advocate for sustainable computing through public outreach, workshops and community partnerships.

Addressing the global e-waste crisis and reducing the carbon produced during operation, and equally, manufacturing, of consumer and datacenter electronics necessitates not only incremental technical improvements, but more broadly, a paradigm shift towards slower and more sustainable computing practices. To contend with these issues, both computer engineers and the general public need a better understanding of how their personal use of computers and their work relate to their social and environmental contexts. We argue that teaching electronic and computer repair is a great place to begin these conversations, by giving students the opportunity to develop practical hands-on skills through experiential, situative learning, and then linking these concrete experiences to more abstract discussions of sustainable computing. We have developed and run a year long course for university students, and workshops aimed at K12 students, both of which center around teaching sustainable computing and hands-on skills through electronic and computer repair. We designed and evaluated this course material based on surveys and interviews with students, repair experts, and community members. In this poster, we present our curricula and course materials and explain the pedagogical theory and research that underpin our approach, as well as how we adapted our work for different student groups and course formats. We enumerate challenges that we encountered while implementing these lessons, and provide recommendations for other educators interested in teaching repair courses or workshops.

In this article, we present Syncopation , a performance-boosting fine-grained timing analysis and adaptive clock management technique for High-Level Synthesis-generated circuits implemented on Field-Programmable Gate Arrays. The key idea is to use the HLS scheduling information along with the placement and routing results to determine the worst-case timing path for individual clock cycles. By adjusting the clock period on a cycle-by-cycle basis, we can increase performance of an HLS-generated circuit. Our experiments show that Syncopation improves performance by 3.2% (geomean) across all benchmarks (up to 47%). In addition, by employing targeted synthesis techniques along with Syncopation, we can achieve 10.3% performance improvement (geomean) across all benchmarks (up to 50%). Syncopation instrumentation is implemented entirely in soft logic without requiring alterations to the HLS-synthesis toolchain or changes to the FPGA, and has been validated on real hardware.

The underlying goal of FPGA architecture research is to devise flexible substrates that implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing, and image processing applications through high-precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: (1) higher computational density and (2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem formulation involving computing nested loops over multiply-accumulate (MAC) operations, which covers many basic linear algebra primitives and standard deep neural network (DNN) kernels. A quantitative methodology for deriving efficient coarse-grained compute block architectures from benchmarks is then proposed together with a family of new embedded blocks, called MLBlocks. An MLBlock instance includes several multiply-accumulate units connected via a flexible routing, where each configuration performs a few parallel dot-products in a systolic array fashion. This architecture is parameterized with support for different data movements, reuse, and precisions, utilizing a columnar arrangement that is compatible with existing FPGA architectures. On synthetic benchmarks, we demonstrate that for 8-bit arithmetic, MLBlocks offer 6× improved performance over the commercial Xilinx DSP48E2 architecture with smaller area and delay; and for time-multiplexed 16-bit arithmetic, achieves 2× higher performance per area with the same area and frequency. All source codes and data, along with documents to reproduce all the results in this article, are available at http://github.com/raminrasoulinezhad/MLBlocks .

Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs) . FPGA vendors and researchers have responded by updating their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating architectural proposals is difficult, however, due to the lack of publicly available benchmark circuits. This paper addresses this problem by presenting an open-source benchmark circuit generator that creates realistic DNN-oriented circuits for use in FPGA architecture studies. Unlike previous generators, which create circuits that are agnostic of the underlying FPGA, our circuits explicitly instantiate embedded blocks, allowing for meaningful comparison of recent architectural proposals without the need for a complete inference computer-aided design (CAD) flow. Our circuits are compatible with the VTR CAD suite, allowing for architecture studies that investigate routing congestion and other low-level architectural implications. In addition to addressing the lack of machine learning benchmark circuits, the architecture exploration flow that we propose allows for a more comprehensive evaluation of FPGA architectures than traditional static benchmark suites. We demonstrate this through three case studies which illustrate how realistic benchmark circuits can be generated to target different heterogeneous FPGAs.

High-level synthesis (HLS) tools improve hardware designer productivity by enabling software design techniques during hardware development. During HLS the delay of paths can only be estimated, so the resulting circuit may suffer from unbalanced computational path delays across clock cycles. Since the maximum operating frequency of circuits is determined statically using the worst-case timing path, unbalanced paths may lead to reduced performance compared to circuits designed at the hardware level. In this paper, we address this using Syncopation, a performance-boosting fine-grained timing analysis and adaptive clock management technique for HLS circuits. The key idea is to use the HLS scheduling information along with the results from placement and routing to determine the worst-case timing path for individual clock cycles. By then adjusting the clock period on a cycle-to-cycle basis, we can increase circuit performance. Our experiments show that Syncopation and fine-grained timing analysis can improve performance without altering the HLS-synthesis toolchain.