A new area model for estimating the layout area of switch blocks is introduced in this work. The model is based on a realistic layout strategy. As a result, it not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers available and the actual dimensions of these metals. The model assigns metal layers to the routing tracks in a way that reduces the number of vias that are needed to connect different routing tracks together while maintaining the tile-based structure of FPGAs. It also takes into account the wiring area required for buffer insertion for long wire segments. The model is evaluated based on the layouts constructed in the ASAP7 FinFET 7nm Predictive Design Kit. We found that the new model, while specific to the layout strategy that it employs, improves upon the traditional active-based area estimation models by considering the growth of the metal area independently from the growth of the active area. As a result, the new model is able to more accurately estimate the layout area by predicting when the metal area will overtake the active area as the number of routing tracks is increased. This ability allows the more accurate estimation of the true layout cost of FPGA fabrics at the early floor planning and architectural exploration stage; and this increase in accuracy can encourage a wider use of custom FPGA fabrics that target specific sets of benchmarks in future SOC designs. Furthermore, our data indicate that the conclusions drawn from several significant prior architectural studies remain to be correct under FinFET geometries and wiring area considerations despite their exclusive use of active-only area models. This correctness is due to the small channel widths, around 30–60 tracks per channel, of the architectures that these studies investigate. For architectures that approach the channel width of modern commercial FPGAs with more than 100–200 tracks per channel, our data show that wiring area models justified by detailed layout considerations are an essential addition to active area models in the correct prediction of the implementation area of FPGAs.

A new area model for estimating the layout area of switch blocks is introduced in this work. The model not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers available and the actual dimension of these metals. The model assigns metal layers to the routing tracks in a way that reduces the number of vias that are needed to connect different routing tracks together while maintaining the tile-based structure of FPGAs. The model is evaluated based on the layouts constructed in ASAP7 FinFET 7nm Predictive Design Kit. We found that the new model improves upon the traditional active-based area estimation models by considering the growth of metal area independently from the growth of the active area. As a result, the new model is able to more accurately estimate layout area by predicting when metal area will overtake active area as the number of routing tracks is increased. This ability allows the more accurate estimation of the true layout cost of FPGA fabrics at the early floor planning and architectural exploration stage; and this increase in accuracy can encourage a wider use of custom FPGA fabrics that target specific sets of benchmarks in future SOC designs.

This work presents the layout area of encoded and decoded multiplexers, two essential building blocks of modern FPGAs, in FinFET. Layouts with both 2 and 3 metal layers based on ASAP7 Predictive Design Kit are presented. The layout area is then compared with the prediction of two equation-based models: the VPR area model and the COFFE area model. We found that, with the original model parameters which are adjusted for planar technologies, these two equation-based models are not accurate in predicting FinFET layout area with error ranges of -2.3% to +86.5% and -32.7% to +19.3% for the VPR and COFFE models, respectively. Furthermore, when the model parameters are specifically adjusted for FinFET, the error ranges remain to be large with -19% to +31% and -26.6% to +25% for the VPR and COFFE models, respectively. These data underline the importance of verifying equation-based models against actual layout areas in FPGA architectural studies, especially when there are significant changes in the underlining process technologies.