Fence region constraints are essential in cell placement, as they can enhance design convergence speed and improve placement quality. This paper introduces a multilevel framework approach to tackle this challenge while maintaining placement quality and reducing complexity. First, the coarsening stage utilizes a fence region aware clustering to avoid inappropriate groupings. Next, recursive quadratic programming is employed to achieve a better initial cell distribution. Previous methods may result in longer wire-length because they typically assign fence objects to their placement regions before distributing cells over a placement region. To mitigate wirelength increases caused by overly restrictive constraints, our refinement stage uses a three-phase approach to gradually adjust the placement regions of fence objects. Additionally, cells are distributed across desired regions using an analytical placement formulation that includes a fence region aware penalty term. Experimental results demonstrate that our methodology achieves improved wirelength and routability while effectively managing fence region constraints.

A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE simulating the two shorted cells with the short defect injected. In this article, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial automatic test pattern generation (ATPG) to generate corresponding test patterns for a given design. A defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using a defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared with a conventional four-way dominance bridge fault model, where four noncollapsible faults at one shorted cell pair are considered for ATPG. In addition, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for four-way dominance bridge faults with more test patterns. The runtime required for extracting 1-time-frame (1tf) defect-based bridge faults has been proven acceptable on industrial designs and some techniques were also proposed to speed up the runtime for extracting 2tf defect-based bridge faults. All experiments in this article are conducted based on industrial designs.

Even though routability is of great concern to a recent global placement algorithm, there still exists a large room to improve it. To make legalization more easier and get a better placement, this article proposes an iterative approach to refine cell locations after global placement, where wirelength and routability are separately optimized in each iteration. It first moves cells to better locations to reduce wirelength. Unlike previous approaches, our approach guarantees that no wirelength will be increased so that the previous optimization result can be better maintained. Moreover, we propose a delicate procedure to move cells according to their gain values to reduce the largest wirelength. Next, the whitespace re-allocation approach is applied to redistribute whitespace over a chip to improve routability without changing relative locations of cells. To ensure that enough space will be allocated to the most routing congestion regions, we propose a sigmoid function to increase routing demands of regions according to their routing overflows and number of pins. The experimental results show that our methodology can obtain shorter wirelength and better routability in industrial designs when compared to other approach.

Parallel asynchronous stochastic dual coordinate descent algorithm (PASSCoDe) is an efficient method to train linear models in multi-core shared-memory systems. PASSCoDe enjoys a good speedup when the number of threads is less than 8 on sparse datasets, i.e., the percentage of nonzero elements in the training data is relatively small. However, due to the memory conflict and delayed parameter access problem in parallel execution, it often diverges or does not converge to the best accuracy as a serial dual coordinate descent algorithm does. In this paper, we propose two algorithms – Adaptive Hybrid algorithm and Lazy-Sync algorithm, to overcome the convergence issues in parallel execution. Both algorithms use the current accuracy to guide the execution and strike a balance between accuracy and efficiency. Experimental results indicate that both algorithms converge to the same high accuracy as a sequential program does on all datasets tested except on an extremely small one. On the other hand, PASSCoDe sometimes converges to a less accurate value or does not converge at all on some datasets. Our methods also outperform PASSCoDe-Fix, an improved version of PASSCoDe, in stable convergence, execution speed, and scalability. For example, the Adaptive Hybrid algorithm runs up to 2.8 times faster than PASSCoDe-Fix, and the Lazy-Sync algorithm runs 11 times faster than PASSCoDe-Fix on dataset covtype with 10 threads.

A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE-simulating the two shorted cells with the short defect injected. In this paper, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial ATPG to generate corresponding test patterns for a given design. Defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared to conventional 4-way dominance bridge fault model, where four non-collapsible faults at one shorted cell pair are considered for ATPG. Also, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for 4-way dominance bridge faults with more test patterns. The experimental result based on industrial designs has demonstrated the effectiveness of using defect-based bridge faults for ATPG while showing an affordable runtime on extracting defect-based bridge faults.