Vector-based dynamic IR-drop analysis of the entire vector set is infeasible due to long runtime. In this paper, we use machine learning to perform vector-based IR drop prediction for all logic cells in the circuit. We extract important features, such as toggle counts and arrival time, directly from the logic simulation waveform so that we can perform vector-based IR-drop prediction quickly. We also propose a feature engineering method, density map, to increase correlation by 0.1. Our method is scalable because the feature dimension is fixed (72), independent of design size and cell library. Our experiments show that the mean absolute error of the predictor is less than 3% of the nominal supply voltage. We achieve more than 495 speedups compared to a popular commercial tool. Our machine learning prediction can be used to identify IR-drop risky vectors from the entire test vector set, which is infeasible using traditional IR-drop analysis.

The demand for neuromorphic chips has skyrocketed in recent years. Thus, efficient manufacturing testing becomes an issue. Conventional testing cannot be applied because some neuromorphic chips do not have scan chains. However, traditional functional testing for neuromorphic chips suffers from long test length and low fault coverage. In this work, we propose a machine learning-based test pattern generation technique with behavior fault models. We use the concept of adversarial attack to generate test patterns to improve the fault coverage of existing functional test patterns. The effectiveness of the proposed technique is demonstrated on two Spiking Neural Network models trained on MNIST. Compared to traditional functional testing, our proposed technique reduces test length by 566x to 8,824x and improves fault coverage by 8.1% to 86.3% on five fault models. Finally, we propose a methodology to solve the scalability issue for the synapse fault models, resulting in 25.7x run time reduction on test pattern generation for synapse faults.

Volume diagnosis and debug play a key role in identifying systematic test failures caused by manufacturing defectivity, design marginalities, and test overkill. However, diagnosis tools often suffer from poor diagnosis resolution. In this paper, we propose techniques to improve diagnosis resolution by test failure clustering and reorganization. The effectiveness of our techniques is demonstrated on two industrial designs in cutting-edge process nodes and verified by targeted analysis and testing. The number of suspects is reduced by 3.1x and 575.2x on average. The proposed techniques can be implemented using existing commercial diagnosis tools with runtime overheads below 1%.

Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool.

Power supply noise induced IR drop can cause transition delay faults (TDF) clustered in a small region. However, traditional diagnosis technique cannot handle clustered multiple TDF very well. This paper proposes a diagnosis tool for clustered multiple TDF. Star tracing for TDF is applied to find possible suspects. To tolerate fault masking and fault reinforcement effects, we propose an approximate covering heuristic to find a group of suspects. During approximate covering, we extract important suspects which are likely to be true suspects. We assume many suspects physically cluster around true suspects so our technique prunes suspects based on this assumption. We use correlation coefficient to determine the optimal number of clusters (Optimal NC) so we can apply the K-means algorithm to group suspects. Finally, we prune the least possible cluster but keep important suspects. Simulation on benchmark circuits shows that average accuracy of our tool (0.80) is much better than that of a commercial tool (0.47). Average resolution of our tool (0.35) is also better than that of the commercial tool (0.23).