In this paper, we present a fully integrated dual-dimensional reconfigurable charge pump (DDR-CP) for energy harvesting (EH) applications. EH systems often encounter significant input voltage variations due to changing environmental conditions, posing a challenge for conventional CPs, which are efficient only at discrete input-to-output voltage ratios. This limitation restricts their performance and efficiency over a wide power dynamic range (PDR). To address this, the proposed DDR-CP incorporates a dual-dimensional reconfiguration approach, optimizing operating frequency and CP stage configuration to maximize system efficiency across varying input and load conditions. A novel frequency tuning mechanism,termeddynamic source feed, is devised. Also, a mathematical analysis of dominant power losses over a wide PDR is derived, providing a robust design guideline for CP optimization. Fabricated in a 65-nm CMOS process, our DDR-CP integrates a total on-chip pumping capacitor of 176 pF within a compact active area of 0.286 mm2. The DDR-CP supports tri-mode operation, handling input voltages from 0.21 V to 0.7 V, and delivers up to$40~\mu $W of output power. Measurement results demonstrate a peak PCE of 73% and an average PCE ranging from 30% to 70% across the entire input range, validated under a 55-K$\Omega $output load.

This article presents a fully integrated tri-band RF energy harvesting system (RFEH) in 65-nm CMOS technology. The system is designed to harvest ambient RF energies at 900 MHz, 1.9 GHz, and 2.4 GHz through a tri-band impedance matching network (IMN), cross-coupled differential-drive (CCDD) rectifier, and an output voltage monitoring circuit to limit the rectified output voltage to 3.3 V. The system achieves a power conversion efficiency (PCE) of over 30 % across all three frequency bands with a peak of 42.8 %. Furthermore, the system exhibits a peak sensitivity of -20 dBm at an output DC voltage of 1$V$output.

This brief reports a dual-topology CMOS rectifier with an extended power dynamic range (PDR) for radio frequency (RF)-based hybrid energy harvesting (RF-HEH) systems. By leveraging both the cross-coupled differential drive (CCDD) and the Dickson topologies with high forward conduction and low reverse leakage, we obtain an extension of the rectifier’s PDR by adaptively disabling the CCDD counterpart and enabling the Dickson counterpart to dominate the rectifier’s performance during high-power operation. Apart from that, we formulate a rectifier-performance index (RPI), which accounts for the power conversion efficiency (PCE), the PDR, the sensitivity, and the load resistance of the rectifier to provide an adequate performance benchmark with the state-of-the-art rectifiers. Fabricated in a 130-nm CMOS, the proposed dual-topology rectifier measures a wide PDR of 19.5 dB with a peak PCE of 78.4% for a 100-$\text{k}\Omega $load operating at 900 MHz. Besides, our prototype records the highest RPI of 19.2 compared to the recent arts operating at GSM900.

This brief proposes a 900-MHz novel CMOS-reconfigurable stack rectifier (RSR) implemented in a three-stage cross-coupled differential rectifier (CCDR) for battery-assist Internet-of-Things (IoT)/wireless sensor network (WSN) applications. A three-mode RSR is incorporated for an extended dynamic range (DR) input power level with a 100-$\text{k}\Omega $load, fabricated in the 130-nm CMOS. The realized RSR achieves a wide DR power conversion efficiency (PCE) by reducing the ON-resistance (${R} _{\mathrm{\scriptscriptstyle ON}}$) in the low-power zone (LPZ) achieved by reducing the threshold voltage (${V} _{\text {th}}$) of the device and alternately increasing${V} _{\text {th}}$in the high-power zone (HPZ) by implementing the proposed reconfigurable stack transistor technique along with the multithreshold voltage (MTV) technique. The circuit observes a measured result of 47.91% in peak PCE at an input power of −14 dBm by driving a 100-$\text{k}\Omega $load. The proposed circuit also achieved 22.8 and 16.3 dB of DR with a PCE over 20% and 30%, respectively. Compared to other state-of-the-art designs, our work exhibits better DR and PCE.

This brief presents a novel circuit architecture for a Dickson-based reconfigurable rectifier with wide power dynamic range (PDR). Besides, a novel figure of merit (FoM) concerning the reconfigurable rectifiers is formulated to provide a more comprehensive assessment of the rectifier’s performance. The proposed reconfigurable design improves the operating range of the rectifier by adaptively switching between the six-stage configuration during low-power operation and the 12-stage configuration during high-power operation. Fabricated in 130-nm CMOS, the proposed reconfigurable rectifier measures a PDR of 14 dB with a peak power conversion efficiency (PCE) of 34.93% for 1-$\text{M}\Omega $load operating at 900 MHz. Relative to the recently published reconfigurable rectifiers, our design records the highest FoM of 36.98 dB/mm2, with minimum harvesting downtime.

This article describes a fully integrated CMOS radio frequency energy-harvesting (RFEH) front end. It features an on-chip stacked step-up transformer integrated with a cross-coupled differential drive (CCDD) rectifier to enhance the input sensitivity. The transformer also serves as an on-chip balun for the CCDD rectifier. The CCDD rectifier innovates a gate-biasing technique and realizes coupling capacitors at the end of each stage to increase the subsequent stage biasing. Here, our RFEH front end operating at 900 MHz achieves an improved sensitivity of −20 and −19.2 dBm at the 1-V output for no-load and a 1-$\text{M}\Omega $load, respectively.