Qiuwei Wang

dblp:277/9778 · DBLP profile ↗
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5ranked-venue papers
0as first author
5since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 since 2021
YearPublicationVenuePosition
2026 An 11.5-bit ENOB 312.5kS/s Column-Parallel Two-Step Single-Slope ADC for Infrared Focal Plane Readout Circuit
Qiuwei Wang, Yiqiang Zhao
ISCAS3
2026 A 7-bit 1-GS/s Single-Channel Charge-Injection Loop-Unrolled SAR ADC with Foreground Calibration
Qiuwei Wang, Mao Ye 0007, Yong Chen 0005
ISCAS4
2026 A 7-bit 1-GS/s Single-Channel Partial Loop-Unrolled SAR ADC Featuring Constant Input Common-Mode for Comparators in 28-nm CMOS
Qiuwei Wang, Yao Li 0024, Mao Ye 0007, Yong Chen 0005
ISCAS3
2024 A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques
abstract
This article presents a novel readout circuit for the resistive tactile sensor array. Based on the 2-D scanning mechanism, a crosstalk suppression technique is proposed by combining the correlated double sampling (CDS) and zero potential method (ZPM). The output of the same sensor under different bias conditions is captured twice and amplified by a channel-parallel fully differential gain stage, performing analogous subtraction. To achieve nonuniformity compensation, the current injected into the readout channel is adjusted by the channel-parallel digital-to-analog converter (DAC). A successive approximation register (SAR) analog-to-digital converter (ADC) performs quantization, and the chip can be used as a serial peripheral interface (SPI) slave to update register values for gain configuration, power consumption control, and nonuniformity compensation. The 180-nm CMOS prototype chip occupies an area of$4.8~\text {mm}^{2}$and consumes$285~\mu $W. In order to validate the design, a tactile sensing system is built, using the readout circuit along with a$10\times 10$flexible sensor array. With the techniques proposed in this article, the readout error of the sensors in array is less than 0.3‰.
Yao Li 0024, Junfeng Geng, Mao Ye 0007, Jiaji He 0001, Xiaoxiao Zheng, Qiuwei Wang, Yiqiang Zhao
IEEE Trans. Very Large Scale Integr. Syst.6
2024 A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR
abstract
This article presents a low noise and wide linear dynamic 20-channel analog front-end (AFE) array for frequency-modulated continuous-wave (FMCW) light detection and ranging (LiDAR) system. Each channel of the AFE array mainly consists of a shunt feedback transimpedance amplifier (SF-TIA) with a dc cancellation loop (DCL), a post amplifier, and an output buffer. The DCL is proposed to eliminate the dc current, comprising the dc current sunk to ground (dc-STG) and the dc current sourced from power supply (dc-SFP). In addition, the post amplifier, cascaded with an operational transconductance amplifier (OTA) and an SF-TIA, is proposed to decouple the relationship between gain and output common voltage, achieving both large gain and large output swing. Furthermore, the equalization technique is adopted to expand the bandwidth of the AFE array. The AFE array was implemented and fabricated in a 0.18-$\mu \text{m}$CMOS technology. Measurement results show that the AFE array achieves the maximum transimpedance gain of 107 dB and eliminates the dc current between −150 and$250 ~\mu \text{A}$. With the maximum transimpedance gain, the measured bandwidth, the equivalent input-referred rms noise current, and the signal-to-crosstalk ratio (SCR) between adjacent channels are 165 MHz, 29.4 nArms, and −33.9 dB, respectively. The AFE array also achieves a linear dynamic range (DR) of 66 dB and the area of each channel is approximately equal to$0.16\times1.3$mm2.
Xiaoxiao Zheng, Mao Ye 0007, Yao Li 0024, Qiuwei Wang, Yiqiang Zhao
IEEE Trans. Very Large Scale Integr. Syst.5