Ferroelectric Superconducting Quantum Interference Devices (Fe-SQUIDs) have recently gained attention as a transformative technology for superconducting computing, offering voltage-controlled switching that is essential for large-scale digital circuits. This unique technology has the potential to drive advancements in cryogenic computing by enabling scalable memory systems and voltage-controlled logic circuits. These innovations are critical for the realization of large-scale quantum computers and hold significant promise for high-performance computing and space exploration. In this article, we explore how Fe-SQUIDs, integrated with heater cryotrons (hTrons), can be harnessed to develop key components of computing systems. These include non-volatile memory, voltage-controlled logic circuits, in-memory matrix-vector multiplication systems, and ternary content-addressable memory. We also examine how changes in the key characteristics of Fe-SQUIDs and hTrons influence the performance of these applications, providing insights into the design and optimization of next-generation superconducting hardware.

Phase transition materials (PTMs) have drawn significant attention in recent years due to their abrupt threshold switching characteristics and hysteretic behavior. Augmentation of the PTM with a transistor has been shown to provide enhanced selectivity (as high as ~107 for Ag/HfO2/Pt) leading to unique circuit-level advantages. Previously, a unipolar PTM, Ag-HfO2-Pt, was reported as a replacement for diodes due to its polarity-dependent high selectivity and hysteretic properties. It was shown to achieve ~50% higher-DC output compared to a diode-based design in a Cockcroft-Walton multiplier circuit. In this article, we take a deeper dive into this design. We augment two different PTMs (unipolar Ag-HfO2-Pt and bipolar VO2) with diode-connected MOSFETs to retain the benefits of hysteretic rectification. Our proposed hysteretic diodes (Hyperdiodes) exhibit a low-forward voltage drop owing to their volatile hysteretic characteristics. However, augmenting a hysteretic PTM with a transistor brings an additional stability concern due to their complex interplay. Hence, we perform a comprehensive stability analysis for a range of threshold voltages (−0.2 V$V_{\mathrm { th}}$$3 {\sigma }$Monte-Carlo variation analysis for a Cockcroft-Walton multiplier considering the nonidealities in the host transistor and the PTM. We observe that, hyperdiode-based design achieves ~20% higher-output voltage compared with the conventional designs within a fixed timeframe ($200~\boldsymbol {\mu }$s).

Superconducting electronics have garnered significant attention recently due to their exceptional speed and energy efficiency. They play a vital role in scaling quantum computers to thousands of qubits and offer unique advantages for high-performance computing and aerospace exploration. However, conventional Josephson junction-based superconducting circuits face scalability challenges due to flux trapping and struggle in driving high load impedances. To address these issues, three-terminal cryotron devices have emerged as a promising alternative. Here, we present a novel approach utilizing two heater cryotron devices to construct an XNOR gate, significantly enhancing the area efficiency of existing superconducting XNOR gates. XNOR logic plays a pivotal role in various applications including adder design, data center operations like copy verification and data encryption/decryption. Our designed XNOR logic gate boasts a substantial improvement in area efficiency compared to existing designs, requiring only two heater cryotron devices instead of the previous requirement of ten cryotron devices, leading to an 80% improvement in device count. This advancement holds promise for further optimizing superconducting circuitry for various applications.

This report presents a design space analysis for the phase transition material (PTM)-augmented magnetic random-access memories (MRAMs) with separate read–write paths. PTM is augmented in parallel with the magnetic tunnel junction (MTJ), improving the read performance along with providing separate read–write paths. Compared to the standard MRAM, PTM-augmented design achieves up to$1.7 \times $boost in cell tunnel magnetoresistance (CTMR),$1.2 \times $increase in read disturb margin (RDM), and${\sim }3.75 \times $increase in sense margin (SM) at the cost of${\sim }4.75 \times $more power consumption. Here, we first discuss the operating region and biasing requirements to achieve performance improvement. Then, we thoroughly explore the design space to put more options on the table for choosing the material and device structure. Finally, we perform the variation analysis where we address the performance and variation immunity tradeoffs. We demonstrate a 1000-point Monte-Carlo analysis to illustrate the effects of process variations on the performance. With lower distinguishability and read stability, the variation tolerance of the design can be improved manifold employing device-circuit co-design methodology and vice versa.

Next-generation quantum computing (QC) systems, comprising thousands of qubits, are envisioned to accommodate the quantum substrate (qubits) and classical components (control processor, and a digital memory block) in a cryogenic (< 4 Kelvin) environment. Such homogeneous integration will pave the way for superconducting interconnects and reduce the noise arising from thermal gradient. However, in the existing QC systems, cryogenic control processors and memory blocks are still operated following the von Neumann architecture. This leads to significant performance overhead due to the repetitive data movement between physically distinct memory and processing units. Thus, it becomes challenging to implement computationally expensive machine learning (ML) algorithms for efficient error correction and control of qubits in a QC. In-memory implementation of ML algorithms at cryogenic temperature can be a game-changer for a practical QC. Here, we demonstrate a unique technique for cryogenic in-memory matrix vector multiplication (MVM), the most frequently performed operation in ML algorithms, utilizing a ferroelectric superconducting quantum interference device (FE-SQUID)-based memory array. FE-SQUID is a promising cryogenic memory device thanks to its non-volatile nature, voltage-controlled switching, scalability, and compatibility with commercially available superconducting device fabrication processes. Moreover, due to having separate read-write paths, the read operation can be optimized without imposing any limit on the read bias and hence, multiple levels of read current with notable separation can be used to map the inputs for the MVM operation. We use an experimentally-calibrated compact model for FE-SQUID to design and test our proposed system. We evaluate FE-SQUID-based in-memory MVM by performing several classification tasks using MNIST handwritten digits, fashion, and emotion datasets. We achieve 93.83%, 80.49%, and 92.5% accuracy for handwritten digits, fashion, and sentiment classifications, respectively.

With surging interest in quantum computing, space applications, and ultra-fast superconducting processors, the need for compatible cryogenic memory systems is skyrocketing. Among several concurrent candidates for cryogenic data storage solutions, quantum anomalous Hall effect (QAHE) devices have garnered immense interest due to having topologically protected variation-tolerant quantum states. The QAHE cells, in addition to being a promising non-volatile storage technology, have several unique properties that make them ideal for in-memory computing operations. In this work, we propose a novel in-memory computing mechanism by harnessing the intrinsic voltage addition property of a QAHE memory array, implemented using twisted bi-layer graphene (tBLG) on hexagonal boron nitride (hBN). In addition, we extensively explore and implement ternary arithmetic operations utilizing the series-connected Hall voltages across devices for the first time. We propose two schemes for in-memory ternary computing namely IMFE and IMSE, and demonstrate balanced scalar multiplication, dot product operations, and ternary half adder with QAHE memory array.

Spiking neural network (SNN) has emerged as the most biologically accurate approach for information encoding in neuromorphic computing. Cryogenic neuromorphic hardware, which offers exceptional energy efficiency and speed, has recently gained enormous attention among the neuromorphic community. An approach to build such neuromorphic hardware is to use a conductance asymmetric superconducting quantum interference device (CA-SQUID) that has non-volatile and variation- robust dual-resistive behavior and thereby, is referred to as a superconducting memristor (SM). Here, we utilize this unique device to design an SM-based artificial synapse topology for neuromorphic applications. The proposed synapse structure, combined with an SM-based neuron, demonstrates neurosynaptic behavior with enhanced reconfigurability. Our design features eight different non-volatile levels of synaptic strength, utilizing combinations of distinct resistance levels of three SMs, exhibiting an estimated programming power of 8.5 pW. This weight storage feature enables better reconfigurability compared to the existing superconducting synapse structures that utilized fixed resistors and inductors. Additionally, this synapse can be further fine-tuned to dynamically access a wide range of synaptic strengths by using an external bias current. Our study provides valuable insights into the system-level integration of the neuron-synaptic architecture.

Negative Capacitance FET (NCFET) is one of the most promising variants of the emerging steep-slope transistors, able to overcome the ?Boltzmann limit'. The ferroelectric layer in the gate stack brings in new dynamics to the transistor operation by amplifying the surface potential. Steeper subthreshold slope, higher ON/OFF ratio, and the possibility to attain negative output conductance provide unique opportunities for NCFET-based circuit design. However, NCFETs inherently possess additional sources of variation, and hence, the promise of performance benefits in the nominal designs must be examined through extensive variation analysis. The non-volatile ferroelectric FETs (FEFETs) are promising candidates for storage-class memory, whereas the volatile NCFETs are suitable for high-speed SRAM design. In this work, we first draw a contrast between the modeling approaches ideal for the non-volatile FEFETs and volatile NCFETs. We then utilize a compact model for NCFET to analyze the design possibilities in an NCFET-based 6-T SRAM cell compared with its conventional counterpart ? both implemented in the 10 nm technology node. We examine the read, write, and hold performance of the SRAM cells through Monte Carlo variation analysis. We show that, even with additional variation induced spread in the device characteristics, NCFET-based SRAM cell can achieve better Static Noise Margin (SNM) during read/hold modes and allows more aggressive supply voltage scaling. The increased hold stability imposes a penalty in the write performance ? forcing design trade-offs.