Ceph portrays a resilient clustered storage solution with supporting object, block, and file storage capabilities with no single point of failure. Despite these qualifications, data confidentiality defines a concern in the system, as authentication and access control are the only data protection security services in Ceph. CephArmor was proposed as a third-party security interface to protect data confidentiality by adding an extra protection layer to data at rest. Despite the added layer, the initial design of the API needed to be more efficient in addressing security and performance simultaneously. In this study, we propose a new architectural design to address the associated issues with the preliminary prototype. Comprehensive performance and security analysis verify the improvement of the proposed method compared to the initial approach. The benchmark result has indicated a 37% improvement on average in IOPS, elapsed time, and bandwidth for the write benchmark compared to the initial model.

the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing field-programmable gate array (FPGA) architecture and CAD to achieve better quality-of-results (QoRs) on DL-based workloads. In this optimization process, benchmark circuits are an essential component; the QoR achieved on a set of benchmarks is the main driver for architecture and CAD design choices. However, current academic benchmark suites are inadequate, as they do not capture any designs from the DL domain. This work presents the second version of our suite of DL acceleration benchmark circuits for FPGA architecture and CAD research, called Koios. This suite of 40 circuits covers a wide variety of accelerated neural networks, design sizes, implementation styles, abstraction levels, and numerical precisions. These benchmarks include 32 DL designs and eight synthetic (proxy) benchmarks. The Koios benchmarks are larger, more data parallel, more heterogeneous, more deeply pipelined, and utilize more FPGA architectural features compared to existing open-source benchmarks. This enables researchers to pinpoint architectural inefficiencies for this class of workloads and optimize CAD tools on more representative benchmarks that stress the CAD algorithms in different ways. In this article, we describe the Koios designs, compare their characteristics to prior FPGA benchmark suites, and present results of running them through the verilog-to-routing (VTR) flow using a recent FPGA architecture model. Finally, we present case studies showing how exploration of DL-optimized FPGA architecture and CAD algorithms can be performed using our new benchmark suite.

The Verilog-to-routing (VTR) front-end interface for Verilog compilation, Odin-II, lacks complete support for the Verilog-2005 standard. However, Odin-II provides complex partial mapping for balancing soft logic and hard blocks. Yosys, an open framework for RTL synthesis, provides extensive support for HDLs. However, the Yosys flow forces the user to decide the discrete circuit implementation manually. This research proposes improving device utilization and simplifying the flow by automating complex logic decisions with architecture awareness. According to VTR architectures, hard/soft logic trade-off decisions and heterogeneous logic inference have become available for such coarse-grained BLIF files. Yosys+Odin-II demonstrates promising results by lowering resource consumption, shrinking final circuit footprint, and reducing overall routed wire length, while other criteria remain approximately the same.

Verilog-to-routing (VTR) provides users with an entire flow from the Verilog circuit description to a final FPGA programming configuration. The VTR front-end interface for Verilog compilation, Odin-II, lacks support for the Verilog-2005 standard. However, Odin-II provides complex partial mapping for balancing soft logic and hard blocks. Yosys, an open framework for RTL synthesis, provides extensive support for HDLs. However, the Yosys flow forces the user to decide the discrete circuit implementation manually. The approach taken by Yosys is to map all discrete components into available hard blocks or to explode them in low-level logic when not available. This research proposes improving device utilization and simplifying the flow by automating complex logic decisions with architecture awareness. Yosys, as a front-end for generating coarse-grained netlists, and Odin-II, as BLIF elaborator and partial mapper, are integrated into the VTR flow. According to VTR architectures, hard/soft logic trade-off decisions and heterogeneous logic inference have become available for such coarse-grained BLIF files. Yosys+Odin-II demonstrates promising results by lowering resource consumption, shrinking final circuit footprint, and reducing overall routed wire length, while other criteria remain approximately the same. The overall VTR flow runtime is imperceptibly reduced with Yosys+Odin-II, while the capability of the VTR flow to synthesize more complex designs is improved, and the control over an intelligent partial mapper is provided for users.

Circuit optimization, in any application, is of high importance since it not only improves the efficiency of the intended purpose but also enhances the quality of the final product. It enables the circuit designer to cater to the specific needs of the customer. For circuit optimization to occur, we need to elaborate these circuits on a primary level and perform synthesis operations. Previous research shows that the investigation of improvements to different Hardware Description Language (HDL) elaboration phases, was completely closed source. Verilog To Routing (VTR) is an open-source Electronic Design Automation (EDA) tool. ODIN II is the VTR synthesizer that parses the input Verilog, elaborates its Abstract Syntax Tree (AST), performs the partial mapping according to the architecture file, and performs optimizations such as unused logic removal. To that end, the hard versus soft logic trade-off aims to optimize the performance of the circuit. This project focuses on using machine learning approaches to make synthesis tools intelligent enough to decide this ratio on their own, without the need for human intervention, and based on some predefined criteria. This paper discusses the criteria for having less latency or less critical path delay in the circuit. Also, it aims at providing this level of intelligence at an earlier stage in the VTR pipeline to make better use of this information.

With the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing FPGA architecture and CAD to achieve better quality-of-results (QoR) on DL-based workloads. In this optimization process, benchmark circuits are an essential component; the QoR achieved on a set of benchmarks is the main driver for architecture and CAD design choices. However, current academic benchmark suites are inadequate, as they do not capture any designs from the DL domain. This work presents a new suite of DL acceleration benchmark circuits for FPGA architecture and CAD research, called Koios. This suite of 19 circuits covers a wide variety of accelerated neural networks, design sizes, implementation styles, abstraction levels, and numerical precisions. These designs are larger, more data parallel, more heterogeneous, more deeply pipelined, and utilize more FPGA architectural features compared to existing open-source benchmarks. This enables researchers to pin-point architectural inefficiencies for this class of workloads and optimize CAD tools on more realistic benchmarks that stress the CAD algorithms in different ways. In this paper, we describe the designs in our benchmark suite, present results of running them through the Verilog-to-Routing (VTR) flow using a recent FPGA architecture model, and identify key insights from the resulting metrics. On average, our benchmarks have 3.7× more netlist primitives, 1.8× and 4.7× higher DSP and BRAM densities, and 1.7× higher frequency with 1.9× more near-critical paths compared to the widely-used VTR suite. Finally, we present two example case studies showing how architectural exploration for DL-optimized FPGAs can be performed using our new benchmark suite.

Verilog-to-Routing (VTR) is a Field-Programmable Gate Array (FPGA) Computer-Aided Design (CAD) tool. It is composed of three tools, namely ODIN II, ABC and VPR with each performing distinctive optimizations at different stages of the design flow. The elaboration and hard block synthesis stage of VTR is the core responsibility of the sub-project ODIN II. This work enables ODIN II to use fewer hard adders in the circuit by allowing soft logic implementation alongside hard logic for circuits featuring addition operations. This is particularly useful in scenarios where a sufficient number of hard blocks are not available. The results of applying our modifications to ODIN II as well as the entire VTR flow have been analysed. The results reveal the potential of current adder optimizations to achieve up to 17% performance gains in terms of critical path delays. Another effect of the optimization is the implications on the resulting device size. Some future prospects in this respect are also outlined in this paper.

Technology mapping is the transformation of a general Boolean logic network into a functional equivalent K-LUT network that can be implemented by the target FPGA device. Because an FPGA architecture is pre-determined, technology mapping is limited to the available resources. However, circuits can be optimized before the low-level synthesis phase. Odin II, part of the Verilog-to-routing project, is responsible for synthesis and elaboration. In the partial mapping phase of Odin II, some modifications are still possible for high-level modules-adder, multiplier-when there is no hard block available. When Odin II performs partial mapping to create soft logic, we can choose which implementation of a high-level module works best with respect to the desired goals: area versus speed. In this paper, we describe a method to modify circuit characteristics based on placement criteria. More specifically, after partial mapping circuit components during Verilog HDL code synthesis, there are still potential modifications in soft-logic circuit generation. We propose using a genetic algorithm during synthesis to adjust soft-logic circuit implementation in order to achieve the desired synthesis goal. We show that the approach provides promising results for a marginal cost in runtime.