Process, Voltage, Temperature (PVT) variations impede the test generation for Small Delay Faults (SDFs) significantly as test patterns effective for one circuit instance may not be valid for a different one. Temperature-induced timing variations in FinFET and Gate-All-Around (GAA) technologies are especially severe due to temperature fluctuations and self-heating. Depending on the supply voltage, they show the Temperature Effect Inversion (TEI) which describes the increase of the circuit speed with increasing temperature. The Zero Temperature Coefficient (ZTC) specifies a supply voltage where TEI approaches 0, and the optimal voltage is determined, such that the effects of temperature-induced variability are minimized. Simulation results are reported, which demonstrate that test generation at the ZTC voltage leads to higher fault coverage of SDFs while using significantly less test patterns.

Many applications allow errors during communication as long as their sizes or rates are limited. These applications are perfect candidates for approximate communication and provide sufficient degrees of freedom to optimize the communicated data for performance, power, reliability and safety within certain error bounds. In this study, we present a novel approach for approximate communication which is specifically tailored to the streaming of data between sensors and control units on narrow parallel buses. To meet the performance goals, the presented approach relies on base-delta compression, where a base value is followed by a sequence of differences to it (deltas). To ensure an efficient low power transmission of data as well as a high reliability and safety at the same time, the approach uses a Gray code for bus encoding and approximates the data within given error bounds, such that crosstalk induced faults and currents are minimized and the overall switching activity is kept low.

Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectiveness of such patterns, different circuit instances may show a different fault coverage for the same test pattern set. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations due to the computational complexity. A statistical learning scheme maximises the coverage of SDFs in circuits following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults (TFs) with fast timing-aware fault simulation on GPUs. Simulation experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detection while the fault coverage even increases.

Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time. To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST. Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.