Neural radiance fields (NeRFs) have transformed 3-D reconstruction and rendering, facilitating photorealistic image synthesis from sparse viewpoints. This work introduces an explicit data reuse neural rendering (EDR-NR) architecture, which reduces frequent external memory accesses (EMAs) and cache misses by exploiting the spatial locality from three phases, including rays, ray packets (RPs), and samples. The EDR-NR architecture features a four-stage scheduler that clusters rays on the basis of$Z$-order, prioritize lagging rays when ray divergence happens, reorders RPs based on spatial proximity, and issues samples out-of-orderly (OoO) according to the availability of on-chip feature data. In addition, a four-tier hierarchical RP marching (HRM) technique is integrated with an axis-aligned bounding box (AABB) to facilitate spatial skipping (SS), reducing redundant computations and improving throughput. Moreover, a balanced allocation strategy for feature storage is proposed to mitigate SRAM bank conflicts. Fabricated using a 40-nm process with a die area of 10.5 mm2, the EDR-NR chip demonstrates a$2.41\times $enhancement in normalized energy efficiency, a$1.21\times $improvement in normalized area efficiency, a$1.20\times $increase in normalized throughput, and a 53.42% reduction in on-chip SRAM consumption compared with state-of-the-art accelerators.

This paper proposes a radio map reconstruction method based on the Neural Architecture Search Enhanced Deep Regularization Model. Traditional radio map reconstruction algorithms face many challenges, such as extremely sparse measurement data and complex wireless signal environments. To solve the problem of unstable output, an external regularizer is introduced to provide additional regularization input in the prediction process to assist the neural network in capturing the explicit prior information from the sparse measurements and performing restoration. Moreover, to ensure the efficiency of capturing implicit prior information, neural architecture search is adopted to optimize the structure of the completion network, further enhancing the robustness of the neural network and the accuracy of reconstruction. The experimental results show that our proposed method is more accurate and stable than the traditional completion methods, especially in the circumstance of a low sampling rate, and can better adapt to the situation of interrupting the probability distribution in unknown regions without a dataset.

In this article, a novel multiuser multiple-input-multiple-output (MIMO) communication system for Internet of Things (IoT) is proposed, where the aerial reconfigurable intelligent surface (ARIS) and nonorthogonal multiple access (NOMA) are used as the sum rate enhancement pathway. The base station (BS) has multiple antennas that transmit superimposed signals to multiple users. The passive ARIS serves as a flexible transmit relay to reduce path loss and improve channel gains. Users are divided into several groups based on their channel status, each sharing a radio frequency (RF) chain. To maximize the sum rate of all users, the placement of ARIS, the passive/active beamforming design and the power allocation among users are jointly optimized. As the joint optimization for user grouping, passive/active beamforming and power distribution is formulated as a mixed-integer nonlinear program (MINLP) which is nonconvex and coupled and hence, obtaining an optimal solution is challenging. In this article, the problem is decoupled into three subproblems and solved alternately efficiently. The numerical results demonstrate that the suggested MIMO-ARIS-NOMA system can achieve higher sum rate performance than traditional schemes.

This study presents a 112-Gb/s four-level pulse-amplitude modulation transmitter implemented in a 28-nm CMOS process. An innovative quasi-voltage-mode driver is proposed, which demonstrates similar bandwidth compared to the current-mode logic driver with an approximately 30% power reduction and provides flexible linearity fine-tuning. The TX architectures with and without the pre-driver stage are optimized to exploit the bandwidth limit further. A three-tap T/2–T variable-spaced feed-forward equalizer is designed to realize reconfigurable 0.5-T, 0.6-T, 0.75-T, and 1-T tap delays, which enables customized eye-opening optimization under different data rates and channel responses. The measurement results show that the energy efficiency of the proposed TX is 0.92 pJ/b with a 0.9-Vppd DC output swing, and the best level separation mismatch ratios are 99.8% and 99.6% at 100-Gb/s and 112-Gb/s, respectively.

Neural rendering, a transformative approach for 3-D scene reconstruction and rendering, has advanced rapidly in recent years. This article introduces an energy-efficient neural rendering coprocessor that implements the popular and widely used instant neural graphics primitive (Instant-NGP) algorithm. In particular, we address the challenges of limited resources for deploying Instant-NGP on edge by proposing a dedicated architecture, which incorporates three main innovations: 1) we optimize occupancy grid queries in the ray marching module by partitioning the grid and decoupling the query process from sampling point generation, which improves both efficiency and memory usage; 2) we introduce a bilinked list-based ray switching strategy, which ensures continuous pipeline utilization to overcome the inefficiencies caused by sequential processing; and 3) we optimize the hash encoding process by incorporating quantization-aware training (QAT), enabling the hash table to fit into on-chip memory, thereby improving performance on resource-constrained devices. To demonstrate the effectiveness of our architecture, we design and fabricate a proof-of-concept chip using 40-nm CMOS technology and develop a testing system to evaluate its performance. Measurement results validate the advantages of the proposed design, showing that our chip achieves superior energy efficiency compared to both server and edge graphics processing units (GPUs), as well as other state-of-the-art neural rendering chip designs.

Expanding upon the foundational Neural Radiance Fields (NeRF) framework, neural rendering techniques have seen wide-ranging applications in 3D reconstruction and rendering. Despite the numerous attempts to accelerate the original NeRF, the ray marching process in many neural rendering algorithms remains a performance bottleneck, constraining their rendering speed. In this work, we introduce an innovative method for effective sampling based on density estimation to alleviate this bottleneck. The proposed method can effectively reduce the number of required occupancy grid access without compromising rendering quality. Evaluation and analysis results validate the effectiveness of the proposed approach, delivering notable improvements in rendering efficiency.

Neural Radiance Fields (NeRF) has attracted growing attention in the fields of 3D reconstruction and rendering. However, straightforward NeRF algorithms encounter challenges in accurately capturing complex surface details with rich high-frequency information. A recent development known as Convolutional Neural Radiance Field (ConvNeRF) has demonstrated state-of-the-art results for these tasks. But it comes with substantial irregular computational requirements, particularly in the convolutional volume rendering phase. In this paper, we introduce a hardware accelerator designed to enhance the efficiency of convolutional volume rendering in ConvNeRF. Our approach includes the creation of specialized computation modules and corresponding on-chip memory system optimized for seamless support of gated convolutions and skip connections in ConvNeRF. To validate our design, we implement it in VerilogHDL and build a prototype using Field Programmable Gate Array (FPGA). We also map our design to 40nm CMOS technology. The evaluation results underscore the superiority of our accelerator in terms of energy efficiency when compared to an implementation on an NVIDIA 2080Ti GPU, offering approximately 84.6× more frames per watt.

Neural Volume Rendering (NVR) has advanced explosively since the advent of Neural Radiance Field (NeRF), a technique for novel view synthesis of complex scenes based on a finite set of input views. Existing ray casting-based NVR approaches process rays concurrently to leverage parallelism but fails to consider its impact on cache locality, which ultimately undermines the efficiency of corresponding dedicated hardware accelerator designs. We further observed that there exhibits spatial correspondence between features and voxels in NVR that can be exploited by processing in the order of voxel, not ray. This paper introduces a novel approach to meticulously reorder the execution of rays, ensuring that rays with similar memory access patterns are processed in parallel, thereby enhancing cache locality. On the basis of that, we also propose an efficient backend architecture and a corresponding memory subsystem, facilitating accurate data prefetching to hide off-chip memory latency. To validate the proposed architecture, we implement our design in VerilogHDL and evaluate the performance by post-synthesis simulation with real scene data. The evaluation results demonstrate that our design markedly enhances the efficiency of NVR processing, achieving a considerable speedup ($1.62\times $) compared to the state-of-the-art NVR accelerator, while necessitating significantly less silicon area ($5.12\times $) and power ($32.79\times $).

Neural Radiance Field (NeRF), a disruptive method for 3D representation and rendering, is extremely popular in the field of computer graphics and computer vision in the past three years. The most distinctive feature of NeRF models is their scene representation property, making it possible to quantize the models according to the complexity of the representing scenes. This paper proposes a novel approach to improve the efficiency of NeRF rendering by adopting precision-scalable computation. We first analyze and validate the idea of scene-dependent quantization for NeRF models. Based on that, we further propose look-up table (LUT) processing element (PE)-based precision-scalable computation unit designs. To evaluate the performance of different precision-scalable computing units, we implement these designs and compare the corresponding area, power, speed and energy efficiency. We also compare the proposed designs with existing approaches as well as the fixed precision approach for NeRF rendering tasks. The comparison results show that energy efficiency can be significantly improved by using precision-scalable computation for NeRF.