The multi-stage charge pump in a zero-crossing-based amplifier (ZCBA) presents complex trade-offs. In this brief, we propose a generalized behavioral model for the ZCBA to quickly predict the optimal charge pump design for a ZCBA based on circuit parameters, without conducting time-consuming transistor-level simulations iteratively. This model enables us to numerically analyze in MATLAB the effects of the circuit parameters, which include the current scaling factor, number of current sources, current value, and input amplitude, on the settling performance including overshoot and settling time. The analysis results conclude that there exists an optimal number of stages that yields the fastest settling time for a given total current and load capacitance. Additionally, the settling time exhibits an asymptotic behavior with respect to the total current. To validate this behavioral model, we designed and simulated a transistor-level ZCBA in a 28-nm CMOS process, demonstrating a good agreement between the model analysis and simulation result.

A charge amplifier incorporates digital circuits as an alternative to the classic analog amplifier to achieve a high open-loop gain to maintain a consistent closed-loop gain over input capacitance variations. The digital-assisted charge amplifier employs a comparator, digital control logic, differential charge pump, current sources, common-mode feedback, and clock generator. A detailed analysis studies the amplifier stability and trade-off between ripple voltage and settling speed. A novel two-step reset scheme and tri-state charge pump minimize the output offset due to ripple residues. Fabricated in a 180-nm CMOS process, the digital-assisted amplifier achieves an open-loop gain of 101 dB, closed-loop gain of$15.0~\mu \text{V}$/e-, input-referred noise of 221$\text{e}^{-}$rms, and output swing of 3 V while consuming 2.19 mW. The amplifier also demonstrates the ability to amplify a dynamic input current using a custom opto-electronic test setup. The amplifier maintains a consistent closed-loop gain across parasitic input capacitance from 6 pF to 94 pF.