Silicon carbide (SiC) power semiconductors are superior to traditional silicon devices due to their higher efficiency and performance, but face challenges related to temperature swings caused by very low thermal capacity, which limits their lifespan. To address this issue, this study proposes control methods to regulate the junction temperature of the SiC devices also referred to as Active Thermal Control (ATC). This approach reduces temperature swings, thereby extending the lifetime of SiC devices. The article examines the practical impact of thermal management implementation. Main goal is to present advantages from system perspective, that can be gained in terms of longer life expectancy by reducing thermal stresses. The benefits were evaluated with three different lifetime models using a high-resolution simulation with a small timestep, that allowed detailed observation of switching behavior and thermal transients at the transistor level. Across all tested models, even a basic temperature management algorithm, implemented without any hardware modifications, resulted in quantifiable improvements.

DC link capacitors in DC/AC inverters can be bulky and expensive. Reducing capacitor size can improve power density and reduce the cost of the inverter. The capacitor size depends on the voltage and current stress experienced by the capacitor in operation. Dimensioning the capacitor current stress for all loads can result in significant oversizing. An optimized dimensioning of the DC link capacitor current stress for a specific load, e.g., the traction machine, and load cycle, e.g., a drive cycle, is presented for a passenger electric vehicle and an electrified heavy-duty truck. The analysis considers two types of traction machines: a permanent magnet synchronous machine (PMSM) and an electrically excited synchronous machine (EESM). Four different DC link designs, two for each application, are evaluated in simulations by considering the capacitor lifetime. Simulation results show that a 25% reduction in capacitor size is possible without negatively affecting the lifetime using the proposed method.

In a 2-level inverter, the DC bus bar links the power module to the DC-link capacitors. During hard switching of the power semiconductor, the stray inductance of the bus bar generates voltage overshoots across the switch and the DC bus. Existing literature primarily investigates the impact of these overshoots on the inverter's electromagnetic emissions. This paper focuses on assessing the effect of voltage overshoots on inverter switching losses through a combination of Double Pulse Test (DPT) simulations, drive cycle simulations, and experimental voltage overshoot analysis. Two bus bar prototypes with a 26% difference in stray inductance were developed for a 2-level inverter. The switching losses of the semiconductor were evaluated over drive cycles, revealing a 0.94% increase in energy losses due to the higher bus bar inductance. In line with that, switch-level DPT results indicated an increase of 1.14%. This suggests that analyzing inverter switching losses through drive cycle simulations is important as voltage spike measurement which shows a considerable amount of switching energy loss. Further, the voltage overshoot analysis reveals a 12% reduction in voltage stress on the switch attributable to stray inductance both in simulation and experiment.

This paper investigates the properties of multi-phase drive systems for electric propulsion systems in terms sizing and drive cycle performance. A multi-phase solution offers improved system safety due to redundancy. A 12 slot 10 poles fractional slot winding machine is chosen due to its promising characteristics in terms of short end-windings and ease for mass production utilizing pre-wound coils. The same machine can be reconfigured to be utilized both in 3-phase, using a single inverter, and in 6-phase mode using two 3-phase inverters. IGBT and SiC based inverter topologies are investigated for both 3-phase and 6-phase systems. In the multiphase mode the capacitor bank current rating can be reduced by 43.5% if PWM carrier shift is exploited. Multiple drive cycle studies are performed. For the 6-phase system a total reduction of electric machine losses of up to 4.6% and up to 3.8% inverter losses are reported.

In automotive applications both space and operational safety of the drive-train are important design considerations. In this study a thorough DC link design for a fault tolerant dual three-phase drive train is conducted. PWM interleaving technique is utilized and based on the three-phase reference case DC link sizing maps in terms of both current and voltage stress are obtained for dual-three-phase configurations.It is found that current stress of the DC link capacitor can be reduced by up to 46 % compared to the three phase case. Similarly, the voltage stress can be reduced by up to 45 % while maintaining fault tolerant capability.