In this paper, a common current control structure in the stationary reference frame, comprising a proportional resonant (PR-)controller and additional resonant control units for harmonic suppression, is applied to a modular multilevel converter (MMC). Discretization of the controllers as well as different control targets in the context of distorted grid quantities are addressed. Current harmonic rejection is achieved applying a resonant band-pass unit to generate the according references for the current control. Simulations are performed to evaluate the designed control.

This paper presents an implementation methodology to model a single delta bridge cell (full-bridge) modular multilevel converter static synchronous compensator (SDBC-MMC-STATCOM) in FPGA based real-time simulator. Mathematical modeling of full-bridge submodule and equivalent circuit-based modeling of single delta bridge cell modular multilevel converter is presented. This paper also discusses about different discretization strategies to convert continuous time equations into z-domain equations for implementation in field programmable gate array (FPGA). The discretized equations are verified by comparing its voltage and current waveforms with its equivalent model developed using the Simscape Electrical Specialized Power Systems library in Simulink. The testing is carried out with 4kV, 2MVA STATCOM model with phase-shifted carrier-based modulation. The model is then implemented in FPGA to perform real-time simulation in OPAL-RT real -time simulator. The tests verify that the real-time model of the STATCOM behaves similar to the Simulink reference model for positive sequence reactive power compensation with no voltage unbalance at the point of common coupling (PCC).

This work analyzes the operation of a Modular Multilevel Converter (MMC) Single Delta Bridge Cell (SDBC) Static Synchronous Compensator (STATCOM) under unbalanced grid conditions based on different sequence extraction methods: Decoupled Double Synchronous Reference Frame (DDSRF), Dual Second Order Generalized Integrator (DSOGI), and Fortescue matrix-based filter in αβ frame. The conventional Voltage Oriented Control (VOC) cannot eliminate the 2ω components caused by unbalanced grid disturbances, which leads to the obstruction of the system along with its control operations. Moreover, under such conditions, the phase-locked loop (PLL) fails to provide an accurate frequency and phase angle of the AC voltage resulting in synchronization failure and non-accurate current injections. Sequence extraction aids the PLL to maintain the synchronization with the grid by following the fundamental component of the voltage positive sequence and allows for the appropriate injection of active and reactive currents. In this paper, the system behavior based on each sequence extraction method is investigated and its impact on the dynamic performances is highlighted through time-domain simulations performed in MATLAB/Simulink.

Modular Multilevel Converter (MMC) has gained popularity in the last decade since it is a transformer-less multilevel converter topology most commonly used in medium and high voltage power conversion applications. There are several component values as well as control parameters which contribute to the operation of MMC. However, the submodule capacitor which is used for energy storage during AC/DC or DC /AC power conversion is one of the most important components in MMC that has a very big impact on the system performance and contributes to large share of the total weight and volume. Under dimensioning the submodule capacitance causes a high capacitor voltage ripple and deteriorate the system performance and on the other hand over dimensioning the submodule capacitance results in higher system cost and system oversize. It is therefore of great importance to dimension the capacitor optimally.