This paper analyzes the requirements for the reporting rate of the live data source to support the operation of Digital Twins (DTs) of Distributed Energy Resources (DERs) for real-time power systems monitoring applications. The visibility of distribution networks is currently limited due to the lack of sufficient measurement and communication infrastructures. With the rapid increase of DERs, it becomes increasingly important to improve the visibility of the distribution networks to ensure the critical system operating constrains are continuously met. DTs are virtual replicas of physical systems, and with certain live measurement data, they can be used to accurately represent the real-time dynamics of the physical entities. The features of DTs could therefore be applied to increase the visibility of network and potentially support real-time decisions making. This paper presents the investigation of the impact of data reporting rate on DT accuracy, based on which, the paper presents a method that could be used to quantify the minimum requirements for data reporting rate to adequately support the DT operation, which provides valuable learning for specifying measurement devices and communication networks to enable DTs-based solutions.

Grid-forming converter establishes a stable and controllable voltage at its output terminal without requiring external angle reference, which enables the GFC to be a candidate for providing black start services. However, this attribute poses significant challenges to the conventional power hardware-in-the-loop (PHIL) simulation, which incorporates the physical power converter by regulating its voltage angle to be synchronized with that of an interfacing power amplifier mimicking the real-time emulated power grid. The lack of voltage synchronization at the coupling point of GFC and interfacing power amplifier leads to instability. To address this challenge, the current-type interfacing method with compensation and scaling scheme is proposed to interface a GFC with soft black-start capability into a PHIL setup. Analytical assessment and experimental results involving interfacing a 90 kVA power converter implemented with grid-forming control are presented to verify the methodology.

Power hardware-in-the-loop (PHIL) simulation leverages the real-time emulation of a large-scale complex power system, while also enabling the in-depth investigation of novel actual power components and their interactions with the emulated power grid. The dynamics and non-ideal characteristics (e.g., time delay, non-unity gain, and limited bandwidth) of the power interface result in stability and accuracy issues within the PHIL closed-loop simulations. In this paper, a compensation method is proposed to compensate for the non-ideal power interface by maximizing its bandwidth, maintaining its unity-gain characteristic, and compensating for its phase-shift over the frequencies of interest. The accuracy of power signals synchronization and the transparency of power transfer within the PHIL configuration are assessed by employing the error metrics. In conjunction with the frequency-domain stability analysis and the time-domain simulations, a case study is made to validate the proposed compensation method.

Power hardware-in-the-loop (PHIL) is a state-of-the-art simulation technique that combines real-time digital simulation and hardware experiments into a closed-loop testing environment. The transportation delay or communication latency impacts the stability and accuracy of PHIL simulations. In this paper, for the purpose of synchronizing the PHIL out-put signal and promoting both the stability and accuracy of PHIL simulation, a hybrid compensation scheme is proposed to compensate for the time delay in the PHIL configuration. A model-based compensator is implemented to shift the time delay out of the PHIL closed-loop to enhance PHIL stability. A time delay compensation model and its equivalent inverse model are employed in the PHIL closed-loop to compensate for the time delay. A phase lead compensator and digital linear-phase frequency sampling filter (FSF) are candidate compensation models to compensate for the time delay and reshape the phase curve on a harmonic-by-harmonic basis. Simulations are made to validate the effectiveness of the compensation scheme.