Introduces a systolic array architecture (SAA) to the design of switched capacitor (SC) filter circuits. Methods of implementing parasitic insensitive systolic SC filters are given. Practical design examples are considered. Simulation results using a circuit extraction program in a LSI/VLSI workstation for a second-order filter are given.>

A stray-insensitive biphase SC realization of an all-pole filter of any desired order is first obtained in the ladder form with all the SCs of equal value. These equal-valued SCs are then replaced by a single time-shared SC. Like any other time-multiplexed circuit, this circuit also requires an increased number of clock phases. Thus against an increase in the die area to generate a multiphase clock on the chip, there is a saving due to the reduction in the total capacitance. One such fifth-order low-pass filter is designed and tested with discrete components to verify its performance.