To use reservoir computing (RC) for practical tasks, both a high memory capacity and nonlinearity are required; however, some RC models have the problem of a low memory capacity. We propose a delay mechanism for increasing the memory capacity in RC as well as a simple and small-scale digital circuit for implementing the delay mechanism. The proposed delay mechanism is integrated into the input layer of the RC model and is expected to be implemented in several RC models, such as material reservoirs and chaotic Boltzmann machine (CBM)-RC. We conducted experiments using a CBM-RC with a delay mechanism (CBM-RC-DL) and evaluated the performance improvement achieved by introducing a delay mechanism. We used CBM-RC as the base model because it is an appropriate model for the hardware implementation of large networks but has a low memory capacity. The experimental results for CBM-RC-DL indicated that the delay mechanism significantly increased the memory capacity of CBM-RC with the addition of a small-scale circuit. Furthermore, the entire synthesized CBM-RC-DL was sufficiently small-scale to be implemented in a field-programmable gate array for edge computing, and it outperformed conventional methods in nonlinear autoregressive moving average 10 (NARMA10)—a benchmark task for time-series data processing. The proposed delay mechanism can facilitate the use of many RC models because of its simple structure.

Artificial general intelligence, which imitates the human brain, is aspired. Episodic memories are considered to be a key feature in building human brain functions. This paper proposes a memory-based entorhinal-hippocampal model that encodes spatial and non-spatial information, essential to realize episodic memories. The model works as a memory that stores the location of objects and events as neural activity packets. This paper also proposes an area-efficient hardware implementation method for field-programmable gate arrays (FPGAs). Our proposal utilizes on-chip random access memories (RAMs) to achieve a large-scale implementation of our model. Circuit simulations validated the behavior of our hardware-friendly model. The results of logic synthesis revealed the area efficiency of the FPGA implementation method that utilizes on-chip RAMs.

In our work, a new area-efficient multiply-accumulation scheme for time-domain neural processing named differential multiply-accumulation is proposed. Our new scheme reduces hardware resources utilization of multiply-accumulation with suppressing the increasing computational time resulting from the time-multiplexing. As a result, 2,048 neurons of fully connected CBM and RC-CBM were synthesized for a single field-programmable gate array (FPGA).