Spin transfer torque magneto-resistive random-access memory (STT-MRAM) has many advantages, such as scalability, persistence, practically infinite endurance, and fast access speed, that make it a promising and emerging technology for memory. However, this technology has multiple reliability issues, such as read and write reliability, higher write power, and long write latency, etc. At elevated temperatures, these issues exacerbate further. As the temperature increases massively in the latest compute nodes, we need to study and understand the effect of temperature on STT-MRAM memory writes and reliability. In this article, we propose the temperature-aware memory controller (MC) and device architecture techniques specific to STT-MRAM technology, which can improve write reliability, retention reliability, and memory power without sacrificing the performance. Our simulation results show that the proposed techniques cumulatively improve the write bit error rate (BER) on an average by$603\times $, increase retention reliability by 65%, along with 27% power reduction and 5.8% improved system performance over the baseline STT-MRAM-based memory subsystem.

Spin-transfer torque magneto-resistive random-access memory (STT-MRAM) is an exciting new emerging technology, being considered as a strong candidate to fill the gaps in the existing memory hierarchy between DRAM and the secondary memory. STT-MRAM has adequate endurance. However, unresolved write switching and read reliability issues still exist at the functional operating temperature corners. One biggest challenge is that the read bit error rate (RBER) is not at an acceptable level for system reliability across the wide operating temperature range. We present an STT-MRAM memory subsystem that is fully compatible with existing DDR-based DIMM designs and evaluate read disturb and read sense bit-error rate (BER) under various operating temperature conditions. We propose temperature aware adaptive techniques for reliable reads at the rank level. The proposed temperature adaptation technique improves overall reliability of the DDR4 STT-MRAM-based memory subsystem with an optimal read current considering an acceptable 64-byte cacheline BER. Our full system simulations show 1000× order of improvements toward a cell raw read disturb BER along with 5% reduction in memory power and less than 1% impact on overall system performance.