This paper presents an energy-efficient ADC-based PAM4 receiver fabricated in a 28 nm CMOS process. The proposed design features a four-way time-interleaved charge-based subranging ADC that integrates three key techniques: 1) a wide input-tolerant charge-based comparator that extends the limited input range and improves operational robustness of conventional low-power charge-based comparators, 2) a conditional-branching-based partial activation scheme that improves the area and capacitive efficiency of the subranging architecture, and 3) a time-based calibration technique that addresses potential performance degradation in the conditional branching scheme. These design techniques enable robust and power-efficient ADC operation optimized for high-speed applications while minimizing the interleaving factor. The prototype ADC achieves an SNDR of 29.1 dB (ENOB = 4.54 bits) at 4 GHz input and 8 GS/s. Operating at 20 Gb/s under a 33.1 dB insertion loss channel, the proposed receiver effectively compensates for ISI, achieving a pre-FEC BER of 1.8E-8 with a competitive energy efficiency of 3.09 pJ/b. These results demonstrate that the proposed low-interleaving architecture provides a scalable and power-efficient solution for high-speed wireline communication.

This paper presents a high-bandwidth memory (HBM) PHY interface employing a reconfigurable differentiator-based crosstalk cancellation (XTC) scheme to mitigate coupling noise arising in high-density silicon interposer channels. By introducing a novel analysis of RC-dominant channels from the perspective of group delay, the proposed XTC achieves precise delay matching by optimal differentiator parameter selection, without requiring additional hardware. Furthermore, the self-loading induced by multiple-aggressor XTC is compensated by reconfiguring the XTC scheme into a bandwidth extension scheme in which the bi-directional signaling nature of HBM interface is leveraged. Additionally, the merged adder with multiple-XTC and decision-feedback equalization (DFE) is proposed to provide improved offset and power performance. Fabricated in a 28-nm CMOS process, the prototype transceiver achieves an edge density of 15 Tb/s/mm and energy efficiency of 0.53 pJ/bit with high-density on-chip channels of 7.5-dB Nyquist loss. The proposed XTC technique reduces the crosstalk-induced jitter (CIJ) by four aggressors by 72.4% at a signal-to-crosstalk ratio of 0.45 dB, achieving an eye-opening of 0.42 UI at a$10^{-12}$bit error rate (BER).

As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodologies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accuracy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm2. The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.

The chip industry is undergoing a market transition from mass production to mass customization. Rapid market changes require agile responses and diversified product designs, particularly in interface circuits managing chip-to-chip communication. To facilitate these shifts, this paper proposes a machine learning-based method for rapidly and accurately predicting and analyzing the performance of high-speed transceivers, along with an evaluation methodology utilizing the proposed approach. Especially, using the process technology information as input in the dataset, this is the first work to predict the performance of a design across different technologies, which will be invaluable in architecting and optimizing designs during the early stages of development. By simulating each functional block, we gather a dataset for parameterized design and performance and incorporate device characteristics from lookup tables. The transmitter, which operates like digital circuits, is trained using parameterized signals with a DNN, while the receiver, containing analog blocks and feedback structures, employs hybrid LSTM-DNN learning with time-series input and output. Our model, trained with a 40 nm design, demonstrates high accuracy in predicting performance even with different foundries and technologies. The majority of performance parameters show an R2value exceeding 0.9, indicating strong predictive accuracy under varying conditions. This method provides valuable insights for early-stage design optimization and process technology scaling, offering potential for broader applications in circuit design areas.

This paper presents an I/O interface with Xtalk Minimizing Affine Signaling (XMAS), which is designed to support high-speed data transmission in high-density interconnects susceptible to crosstalk. The operating principles of XMAS are elucidated through rigorous analyses, and its advantages over existing signaling are validated through numerical experiments. XMAS not only demonstrates exceptional crosstalk removing capabilities but also exhibits robustness against noise, especially simultaneous switching noise. Fabricated in a 28-nm CMOS process, the prototype XMAS transceiver achieves a wire density of 3.6TB/s/mm and an energy efficiency of 0.65pJ/b. Compared to the single-ended signaling, the crosstalk-induced peak-to-peak jitter of the received eye with XMAS is reduced by 75% at 10GS/s/pin data rate, and the horizontal eye opening extends to 0.2UI at a bit error rate$\lt 10{^{-12}}$.

Private inference using homomorphic encryption has gained a great attention to leverage powerful predictive models, e.g., deep convolutional neural networks (CNNs), in the area where data privacy is crucial, such as in healthcare or medical services. Processing convolution layers, however, occupies a huge portion (more than 85 %) of the total latency for private CNN inference. To solve this issue, this paper presents Hyena utilizing a novel homomorphic convolution algorithm that provides speedup, communication cost, and storage saving. We first note that padded convolution provides the advantage of model storage saving, but it does not support output channel packing, thereby increasing the amount of computation and communication. We address this limitation by proposing a novel plaintext multiplication algorithm using the Walsh-Hadamard matrix. Furthermore, we propose the optimization techniques to significantly reduce the latency of the proposed convolution by selecting the optimal encryption parameters and applying lazy reduction. Overall, Hyena achieves 1.6--3.8× speedup and reduces the weight storage by 2000--8000× compared to the conventional convolution. For deep CNNs like VGG-16, ResNet-20, and MobileNetV1 on ImageNet, Hyena reduces the end-to-end latency by 1.3--2.5×, the memory usage by 2.1-7.9× and communication cost by 1.4--1.5× compared to conventional method.

An increase in the data rate of memory interfaces causes higher inter-symbol interference (ISI). To mitigate ISI, recent high-speed memory interfaces have started employing complex datapath, utilizing equalization techniques such as continuous-time linear equalizer and decision-feedback equalizer. This incurs huge overhead for design verification with conventional methods using transient simulation. This paper proposes a fast and accurate verification methodology to evaluate the voltage and timing margin of the interface, based on the impulse sensitivity function. To take nonlinear circuit behavior into account, the small- and large-signal responses were separately calculated to improve accuracy, using the data obtained from the periodic AC and periodic steady-state analyses. This approach achieves high accuracy, with shmoo similarity rates of over 95 %, while also significantly reducing verification time, up to 23 × faster. Moreover, two different methods are proposed for evaluating the multi-stage Rx performance, providing a trade-off between accuracy and efficiency that can be tailored to the specific purpose, e.g., the verification or design process.

This paper presents a 48-Gb/s single-ended PAM-4 receiver (RX) with an adaptive nonlinearity compensating equalizer. The receiver incorporates 3 parallel Cherry-Hooper continuous-time linear equalizers (CTLEs) and a 1-tap 9-coefficient adaptive decision feedback equalizer (DFE). CTLEs provide a variable gain with offset-canceling calibration. The DFE detects the level separation mismatch ratio (RLM) of the transmitted data and nonlinear distortion within the receiver analog front-end (AFE). The nonlinearity is compensated by simultaneously adapting 9 coefficients of the nonlinearity compensator. The proposed RX is fabricated in the 40nm CMOS technology, occupying 0.236 mm2. Measured in a 7-dB loss channel, the RX achieves a BER of less than 10−12and energy efficiency of 2.97 pJ/b.

Due to the fundamental limit to reducing power consumption of running deep learning models on von-Neumann architecture, research on neuromorphic computing systems based on low-power spiking neural networks using analog neurons is in the spotlight. In order to integrate a large number of neurons, neurons need to be designed to occupy a small area, but as technology scales down, analog neurons are difficult to scale, and they suffer from reduced voltage headroom/dynamic range and circuit nonlinearities. In light of this, this paper first models the nonlinear behavior of existing current-mirror-based voltage-domain neurons designed in a 28nm process, and show SNN inference accuracy can be degraded by the effect of neuron’s nonlinearity. Then, to mitigate this problem, we propose a novel neuron, which processes incoming spikes in the time domain and greatly improves the linearity, thereby improving the inference accuracy compared to the existing voltage-domain neuron. Tested on the MNIST dataset, the inference error rate of the proposed neuron differs by less than 0.1% from that of the ideal neuron.

Sensors in mobile devices and IoT systems increasingly generate data that may contain private information of individuals. Generally, users of such systems are willing to share their data for public and personal benefit as long as their private information is not revealed. A fundamental challenge lies in designing systems and data processing techniques for obtaining meaningful information from sensor data, while maintaining the privacy of the data and individuals. In this work, we explore the feasibility of providing local differential privacy on ultra-low-power systems that power many sensor and IoT applications. We show that low resolution and fixed point nature of ultra-low-power implementations prevent privacy guarantees from being provided due to low quality noising. We present techniques, resampling and thresholding, to overcome this limitation. The techniques, along with a privacy budget control algorithm, are implemented in hardware to provide privacy guarantees with high integrity. We show that our hardware implementation, DP-Box, has low overhead and provides high utility, while guaranteeing local differential privacy, for a range of sensor/IoT benchmarks.