It is shown that reverse software engineering using the Unified Process (UP) and visual models with the Unified Modeling Language can be applied to Web site maintenance. By reverse engineering the current Web sites, the implementation models of the current Web sites are derived from the Web sites. For the navigation schemes, the Web elements and their dependencies of the current Web sites are shown in component diagrams. Also, the physical directory structures are shown in the component view of the implementation model. Our empirical results on official university Web site maintenance show that the reverse software engineering and visual models can help Web administrators to understand the navigation schemes and physical structures quickly and easily.

The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism. Instead, wide bit-fields containing net-values for several different times are used to resolve out-of-order events. Bit-parallel operations are performed to simulate gates at the required times. The MDP technique was originally designed to be implemented in hardware, but the current software version of the algorithm has proven to be competitive with conventional event-driven multidelay simulation. Two versions of the MDP technique are presented in this paper, fixed alignment and variable alignment. The fixed alignment algorithm provides bit-fields that are wide enough to capture any event that could occur during the simulation of an input vector, while the variable alignment algorithm uses a minimum-width bit field which is just wide enough to capture those events that could occur at an individual step in the simulation. A prototype hardware design is discussed briefly.

The gateway technique is a method for switching segments of code into and out of the instruction stream. When added to the straight-line code generated by a compiled simulator, gateways can be used to enhance the performance of the generated code by switching only those segments of code that actually need to be executed into the instruction stream. The convergence algorithm is an oblivious compiled code algorithm that can be used with many different types of circuits, including cyclic asynchronous circuits. In its oblivious form, the convergence algorithm provides only modest gains in performance over interpreted event-driven simulation, but with the addition of gateways, the performance of the algorithm increases significantly. Experimental data shows that with gateways, the convergence algorithm runs in about 1/5th the time required for an interpreted event-driven simulation. Additional work has been done to reduce the amount of code generated by the convergence algorithm, and to enhance the locality of the code to improve its performance on machines with caches. When used with a multi-delay algorithm, gateways allow simulations to be performed in 1/3 the time required by interpreted simulations. Gateways also allow zero-delay simulations to be more responsive to the activity rate of the circuit, and allow event driven simulations to outperform levelized compiled code when the activity rate of the circuit falls below 13%.>

The multi-delay parallel (MDP) technique is a multi-delay logic simulation algorithm that uses no event-sorting mechanism. Wide bit-fields and bit-parallel operations are used to resolve out-of-order events. Although the MDP technique was designed to be implemented in hardware, the software version has proven to be competitive with ordinary multi-delay simulation. Two versions of the MDP technique are presented: fixed alignment and variable alignment. The fixed alignment algorithm uses bit-fields that are wide enough to capture any event that could occur during the simulation, while the variable alignment algorithm uses a minimum-width bit field.