Demo Data from EDBT 2026 / reviewers in the wild / expert
Fritz H. Gaensslen
dblp:28/1871
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 100% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › semiconductor devices
device scaling |
0.0 | 1 | 1999 | Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions · Proc. IEEE 1999 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1983 | An Efficient Numerical Algorithm for Simulation of MOS Capacitance · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Methods — techniques the papers use, named apart from their topics
two-dimensional current transport model · 0.0one-dimensional doping profile model · 0.0numerical capacitance evaluation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | Design Of Ion-implanted MOSFET's with Very Small Physical DimensionsabstractThis paper considers the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1 .Scaling relationships are presented which show how a conventional MOS-FET can be reduced in size.An improved small device structure is presented that uses ion implantation to provide shallow source and drain regions and a nonuniform substrate doping profile.Onedimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic.A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations.Polysilicon-gate MOSFET's with channel lengths as short as 0.5 were fabricated, and the device characteristics measured and compared with predicted values.The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected. I. LIST OF SYMBOLSInverse semilogarithmic slope of subthreshold characteristic.Width of idealized step function profile for channel implant.Work function difference between gate and substrate.Dielectric constants for silicon and silicon dioxide.Drain current.Boltzmann's constant.Unitless scaling constant.MOSFET channel length.Effective surface mobility.Intrinsic carrier concentration.Substrate acceptor concentration.Band bending in silicon at the onset of strong inversion for zero substrate voltage.Built-in junction potential. Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, Andre R. Leblanc |
Proc. IEEE | 2 |
| 1991 | Liquid Nitrogen CMOS for Computer ApplicationsabstractPast and present development in the field of operating microelectronic computer circuits at liquid nitrogen temperature (LNT) are reviewed. To assess the potential of this technology, its advantages and disadvantages are discussed. The fact that devices and materials behave generically better at low temperature will have some bearing on the ultimate attainable technology limits. The optimized complementary metal oxide semiconductor (CMOS) system advantages at LNT are analyzed. The basic conclusion is that the liquid nitrogen CMOS (LNCMOS) is a viable system technology for commercial and military computer systems.> Fritz H. Gaensslen, David D. Meyer |
ICCD | 1 |
| 1983 | An Efficient Numerical Algorithm for Simulation of MOS CapacitanceabstractA new, computationally efficient method for the numerical evaluation of the equilibrium capacitance of one-dimensional MOS structures is presented. Capacitance-voltage (C-V) characteristics for arbitary impurity profiles and interface state distributions can be calculated for temperatures ranging from 50 K to 350 K. Examples of simulated C-V characteristics demonstrate the capability of the computer program MOSCAP using these techniques. Richard C. Jaeger, Fritz H. Gaensslen, Sherra E. Diehl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |